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73S8024RN-ILR/F1 PDF预览

73S8024RN-ILR/F1

更新时间: 2024-01-31 11:52:54
品牌 Logo 应用领域
美信 - MAXIM 光电二极管
页数 文件大小 规格书
27页 448K
描述
Analog Circuit, 1 Func, PDSO28, LEAD FREE, SOP-28

73S8024RN-ILR/F1 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:LEAD FREE, SOP-28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.96
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDSO-G28
长度:17.907 mm湿度敏感等级:3
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:2.79 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.493 mmBase Number Matches:1

73S8024RN-ILR/F1 数据手册

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DS_8024RN_020  
73S8024RN Data Sheet  
2 System Controller Interface  
Three separated digital inputs allow direct control of the card interface from the host as follows:  
Pin CMDVCC: When low, starts an activation sequence.  
Pin RSTIN: controls the card Reset signal (when enabled by the sequencer).  
Pin 5V/#V: Defines the card voltage.  
Card clock is controlled by four digital inputs:  
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock  
frequency (crystal or external clock).  
CLKSTOP (active high) allows card power down mode by stopping the card clock.  
CLKLEV defines the card clock level of the card power down mode.  
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the  
card presence only (Low = No card in the reader). When CMDVCC is set low (Card activation sequence  
requested from the host), low level on OFF means a fault has been detected (e.g. card removal during  
card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation  
sequence.  
Rev. 2  
7
 

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