DS_1217F_002
73S1217F Data Sheet
Tables
Table 1: 73S1217 Pinout Description ........................................................................................................... 8
Table 2: MPU Data Memory Map ............................................................................................................... 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers.......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................ 18
Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19
Table 8: XRAM Special Function Registers Reset Values......................................................................... 20
Table 9: PSW Register Flags...................................................................................................................... 22
Table 10: Port Registers .............................................................................................................................22
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 24
Table 12: The MCLKCtl Register................................................................................................................ 24
Table 13: The MPUCKCtl Register............................................................................................................. 25
Table 14: The INT5Ctl Register .................................................................................................................. 31
Table 15: The MISCtl0 Register.................................................................................................................. 31
Table 16: The MISCtl1 Register.................................................................................................................. 32
Table 17: The MCLKCtl Register................................................................................................................ 33
Table 18: The PCON Register.................................................................................................................... 34
Table 19: The IEN0 Register ...................................................................................................................... 36
Table 20: The IEN1 Register ...................................................................................................................... 37
Table 21: The IEN2 Register ...................................................................................................................... 37
Table 22: The TCON Register .................................................................................................................... 38
Table 23: The T2CON Register .................................................................................................................. 38
Table 24: The IRCON Register................................................................................................................... 39
Table 25: External MPU Interrupts.............................................................................................................. 39
Table 26: Control Bits for External Interrupts.............................................................................................. 40
Table 27: Priority Level Groups .................................................................................................................. 40
Table 28: The IP0 Register......................................................................................................................... 40
Table 29: The IP1 Register......................................................................................................................... 41
Table 30: Priority Levels..............................................................................................................................41
Table 31: Interrupt Polling Sequence.......................................................................................................... 41
Table 32: Interrupt Vectors ......................................................................................................................... 41
Table 33: UART Modes ..............................................................................................................................42
Table 34: Baud Rate Generation ................................................................................................................ 42
Table 35: The PCON Register.................................................................................................................... 43
Table 36: The BRCON Register ................................................................................................................. 43
Table 37: The MISCtl0 Register.................................................................................................................. 44
Table 38: The S0CON Register.................................................................................................................. 45
Table 39: The S1CON Register.................................................................................................................. 46
Table 40: The TMOD Register.................................................................................................................... 47
Table 41: Timers/Counters Mode Description ............................................................................................ 48
Table 42: The TCON Register .................................................................................................................... 49
Table 43: The IEN0 Register ...................................................................................................................... 50
Table 44: The IEN1 Register ...................................................................................................................... 50
Table 45: The IP0 Register......................................................................................................................... 51
Table 46: The WDTREL Register ............................................................................................................... 51
Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 52
Table 48: UDIR Control Bit ......................................................................................................................... 52
Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 52
Table 50: The USRIntCtl1 Register ............................................................................................................ 53
Table 51: The USRIntCtl2 Register ............................................................................................................ 53
Table 52: The USRIntCtl3 Register ............................................................................................................ 53
Table 53: The USRIntCtl4 Register ............................................................................................................ 53
Table 54: The RTCCtl Register................................................................................................................... 55
Table 55: The 32-bit RTC Counter.............................................................................................................. 56
Table 56: The 24-bit RTC Accumulator ...................................................................................................... 56
Table 57: The 24-bit RTC Trim (sign magnitude value) ............................................................................. 56
Rev. 1.2
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