Datasheet > 73M1903-IGV/F

73M1903-IGV/F

更新时间： 2024-02-13 15:02:04

品牌	Logo	应用领域
TERIDIAN		/
页数	文件大小	规格书
45页	447K
描述
Consumer Circuit, PQFP32, LEAD FREE, TQFP-32

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73M1903-IGV/F 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	LEAD FREE, TQFP-32	Reach Compliance Code：	unknown
风险等级：	5.59	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G32	长度：	7 mm
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
Base Number Matches：	1

73M1903-IGV/F 数据手册

73M1903

Modem Analog Front End

DATA SHEET

SERIAL INTERFACE

The serial data port is a bi-directional port that can be supported by most DSPs. Although the 73M1903

is a peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a

serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that

can be programmed by the user. The serial bit clock is always derived by dividing the system clock by 18.

The sclk rate, Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs

or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the

rate at which both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout

this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to facilitate

discussions. They are:

1. Fxtal₁= 27MHz, Fs₁= 7.2kHz

2. Fxtal₂= 18.432MHz, Fs₂= 8kHz.

3. Fxtal₃= 24.576MHz, Fs₃= 9.6kHz – chip default.

Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal

frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.

Examples:

1. If Fxtal₁= 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.

2. If Fxtal₂= 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.

3. If Fxtal₃= 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.

When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the

system clock will transition to the PLL-based clock in a glitch-less manner.

Examples:

1. If Fs₁= 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.

2. If Fs₂= 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.

3. If Fs₃= 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.

This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front

end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a

designated serial port register – location bit 7, 0Eh. The transition should be forced on or after the

second Frame Synch period following the write to a designated PLL programming register (0Dh).

When reprogramming the PLL the host should first transition the system clock to the crystal before

reprogramming the PLL so that any transients associated with it will not adversely impact the serial port

communication.

Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),

ENFE=0.

During the normal operation, a data FS is generated by the 1903 at the rate of Fs. For every data FSB

there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin

programmable for type. FS can either be early or late determined by the state of the TYPE input pin.

When Type pin is left open, an early FS is generated in the bit clock prior to the first data bit transmitted

ge: 6 of 45

Rev 1.4

1...3 4 567 8 9...45

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与73M1903-IGV/F相关器件

型号	品牌	描述	获取价格	数据表
73M1903-IM	TDK	Modem, PQCC32	获取价格
73M1903-IM	TERIDIAN	Consumer Circuit, QFN-32	获取价格
73M1903-IM/F	TERIDIAN	Modem Analog Front End	获取价格
73M1903-IM/F	TDK	Modem, PQCC32	获取价格
73M1903-IMR/F	TERIDIAN	Modem Analog Front End	获取价格
73M1903-IVT/F	TERIDIAN	Modem Analog Front End	获取价格

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