Datasheet > 电信电路 > 调制解调器> 73K224L-28IH/F

73K224L-28IH/F

更新时间： 2024-01-01 00:00:42

品牌	Logo	应用领域
TERIDIAN		调制解调器电信电路
页数	文件大小	规格书
31页	243K
描述
Single-Chip Modem

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73K224L-28IH/F 技术参数

生命周期：	Obsolete	包装说明：	LEAD FREE, PLASTIC, LCC-28
Reach Compliance Code：	unknown	风险等级：	5.58
数据速率：	2.4 Mbps	JESD-30 代码：	S-PQCC-J28
长度：	11.54 mm	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
座面最大高度：	4.191 mm	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	MODEM	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.54 mm
Base Number Matches：	1

73K224L-28IH/F 数据手册

73K224L

V.22bis, V.22, V.21, Bell 212A, 103

Single-Chip Modem

DATA SHEET

DTE USER INTERFACE

NAME

TYPE DESCRIPTION

EXCLK

External Clock. This signal is used in synchronous transmission when the

external timing option has been selected. In the external timing mode the rising

edge of EXCLK is used to strobe synchronous transmit data available on the

TXD pin. Also used for serial control interface.

RXCLK

Receive Clock. Tri stateable. The falling edge of this clock output is coincident

Tristate with the transitions in the serial received data output. The rising edge of RXCLK

can be used to latch QAM or DPSK valid output data. RXCLK will be active as

long as a carrier is present.

RXD

Received Digital Data Output. Serial receive data is available on this pin. The

Weak data is always valid on the rising edge of RXCLK when in synchronous mode.

Pull-up RXD will output constant marks if no carrier is detected.

TXCLK

Transmit Clock. Tri stateable. This signal is used in synchronous transmission to

Tristate latch serial input data on the TXD pin. Data must be provided so that valid data is

available on the rising edge of the TXCLK. The transmit clock is derived from

different sources depending upon the synchronization mode selection. In Internal

Mode the clock is generated internally. In External Mode TXCLK is phase locked

to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin.

TXCLK is always active.

TXD

Transmit Digital Data Input. Serial data for transmission is input on this pin. In

synchronous modes, the data must be valid on the rising edge of the TXCLK

clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is

necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended

overspeed mode.

ANALOG INTERFACE AND OSCILLATOR

RXA

TXA

Received modulated analog signal input from the phone line.

Transmit analog output to the phone line.

XTL1

XTL2

These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel

mode crystal. Two capacitors from these pins to ground are also required for

proper crystal operation. Consult crystal manufacturer for proper values. XTL2

can also be driven from an external clock.

I/O

Page: 5 of 31

Rev 7.1

1 2 3 456 7 8...31

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73K224L-28IHR/F	TERIDIAN	Single-Chip Modem	获取价格
73K224L-32IH	SST	Modem, 2.4kbps Data, PQCC32	获取价格
73K224L-IG	SST	Modem, 2.4kbps Data, PQFP52	获取价格
73K224L-IGT	TDK	V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem	获取价格
73K224L-IGT	SST	Modem, 2.4kbps Data, PQFP64	获取价格
73K224L-IH	TDK	V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem	获取价格

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