73K224BL

更新时间： 2024-02-26 22:06:04

品牌	Logo	应用领域
TERIDIAN		调制解调器
页数	文件大小	规格书
33页	202K
描述
Single-Chip Modem w/ Integrated Hybrid

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技术参数
数据手册

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73K224BL 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
长度：	27.686 mm	功能数量：	1
端子数量：	22	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

73K224BL 数据手册

73K224BL

V.22bis, V.22, V.21, Bell 212A, 103

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

PARALLEL MICROPROCESSOR INTERFACE (continued)

NAME

TYPE

DESCRIPTION

WRITE: A low on this informs the 73K224BL that data is available

on AD0-AD7 for writing into an internal register. Data is latched

on the rising edge of WR. No data is written unless both WR and

the latched CS are low.

SERIAL MICROPROCESSOR CONTROL INTERFACE MODE

NAME

TYPE

DESCRIPTION

AD0-AD2

5-7

addresses and should be valid during any read or write

operation.

DATA (AD7)

I/O

SERIAL CONTROL DATA: Data for a read/write operation is

clocked in or out on the falling edge of the EXCLK pin. The

direction of data flow is controlled by the RD pin. RD low outputs

data. RD high inputs data.

READ: A low on this input informs the 73K224BL that data or

status information is being read by the processor. The falling

edge of the RD signal will initiate a read from the addressed

EXCLK in order to read all eight bits of the referenced register.

Read data is provided LSB first. Data will not be output unless

the RD signal is active.

WRITE: A low on this input informs the 73K224BL that data or

status information has been shifted in through the DATA pin and

is available for writing to an internal register. The normal

procedure for a write is to shift in data LSB first on the DATA pin

for eight consecutive falling edges of EXCLK and then to pulse

WR low. Data is written on the rising edge of WR.

NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the register address.

Page: 6 of 33

Rev 7.1

1...3 4 567 8 9...33

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