5秒后页面跳转
73K224BL PDF预览

73K224BL

更新时间: 2024-01-28 03:07:19
品牌 Logo 应用领域
TERIDIAN 调制解调器
页数 文件大小 规格书
33页 202K
描述
Single-Chip Modem w/ Integrated Hybrid

73K224BL 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:22
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.04其他特性:FULL DUPLEX
数据速率:2.4 MbpsJESD-30 代码:R-PDIP-T22
长度:27.686 mm功能数量:1
端子数量:22最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:5.08 mm标称供电电压:5 V
表面贴装:NO电信集成电路类型:MODEM
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

73K224BL 数据手册

 浏览型号73K224BL的Datasheet PDF文件第1页浏览型号73K224BL的Datasheet PDF文件第2页浏览型号73K224BL的Datasheet PDF文件第4页浏览型号73K224BL的Datasheet PDF文件第5页浏览型号73K224BL的Datasheet PDF文件第6页浏览型号73K224BL的Datasheet PDF文件第7页 
73K224BL  
V.22bis, V.22, V.21, Bell 212A, 103  
Single-Chip Modem w/ Integrated Hybrid  
DATA SHEET  
Hz (answer, mark and space). Demodulation involves  
detecting the received frequencies and decoding them  
into the appropriate binary value. The rate converter  
The synch/asynch converter also has an extended  
overspeed mode, which allows selection of an output  
overspeed range of either +1% or +2.3%. In the  
extended overspeed mode, stop bits are output at 7/8  
rising edge of TXCLK the normal width.  
and  
scrambler/descrambler  
are  
automatically  
bypassed in the FSK modes.  
Both the synch/asynch rate converter and the data  
descrambler are automatically bypassed in the  
FSK modes.  
PASSBAND FILTERS AND EQUALIZERS  
High and low band filters are included to shape the  
amplitude and phase response of the transmit and  
receive signals and provide compromise delay  
equalization and rejection of out-of-band signals.  
Amplitude and phase equalization are necessary to  
compensate for distortion of the transmission line and  
to reduce intersymbol interference in the band limited  
receive signal. The transmit signal filtering  
corresponds to a 75% square root of raised Cosine  
frequency response characteristic.  
SYNCHRONOUS MODE  
Synchronous operation is possible only in the  
QAM or DPSK modes. Operation is similar to that  
of the asynchronous mode except that data must  
be synchronized to a provided clock and no  
variation in data transfer rate is allowable. Serial  
input data appearing at TXD must be valid on the  
rising edge of TXCLK.  
ASYNCHRONOUS MODE  
TXCLK is an internally derived 1200 or 2400 Hz  
signal in internal mode and is connected internally  
to the RXCLK pin in slave mode. Receive data at  
the RXD pin is clocked out on the falling edge of  
RXCLK. The asynch/synch converter is bypassed  
when synchronous mode is selected and data is  
transmitted at the same rate as it is input.  
The asynchronous mode is used for communication  
with asynchronous terminals which may communicate  
at 600,1200, or 2400 bit/s +1%, -2.5% even though the  
modem’s output is limited to the nominal bit rate ±.01%  
in DPSK and QAM modes. When transmitting in this  
mode the serial data on the TXD input is passed  
through a rate converter which inserts or deletes stop  
bits in the serial bit stream in order to output a signal  
that is the nominal bit rate ±.01%. This signal is then  
routed to a data scrambler and into the analog  
modulator where quad-bit/di-bit encoding results in the  
output signal. Both the rate converter and scrambler  
can be bypassed for handshaking, and synchronous  
operation as selected. Received data is processed in a  
similar fashion except that the rate converter now acts  
to reinsert any deleted stop bits and output data to the  
terminal at no greater than the bit rate plus 1%. An  
incoming break signal (low through two characters) will  
be passed through without incorrectly inserting a stop  
bit.  
PARALLEL BUS CONTROL INTERFACE MODE  
Eight 8-bit registers are provided for control, option  
select, and status monitoring. These registers are  
addressed with the AD0, AD1, and AD2  
multiplexed address lines (latched by ALE) and  
appear to a control microprocessor as seven  
consecutive memory locations. Six control  
registers are read/write memory. The detect and  
ID registers are read only and cannot be modified  
except by modem response to monitored  
parameters.  
Page: 3 of 33  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1  

与73K224BL相关器件

型号 品牌 描述 获取价格 数据表
73K224BL-32IH TDK Modem, 2.4kbps Data, PQCC32, PLASTIC, LCC-32

获取价格

73K224BL-IGT ETC Single-Chip Modem w/ Integrated Hybrid

获取价格

73K224BL-IH ETC Single-Chip Modem w/ Integrated Hybrid

获取价格

73K224BL-IH/F TERIDIAN Single-Chip Modem w/ Integrated Hybrid

获取价格

73K224BL-IHR/F TERIDIAN Single-Chip Modem w/ Integrated Hybrid

获取价格

73K224L TERIDIAN Single-Chip Modem

获取价格