73K224AL

更新时间： 2024-02-25 07:39:33

品牌	Logo	应用领域
东电化 - TDK		调制解调器
页数	文件大小	规格书
26页	274K
描述
V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid

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技术参数
数据手册

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73K224AL 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
长度：	27.686 mm	功能数量：	1
端子数量：	22	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

73K224AL 数据手册

73K222BL

V.22, V.21, Bell 212A, Bell 103

Single-Chip Modem with Integrated Hybrid

DTE USER

NAME

TYPE

DESCRIPTION

EXCLK

External Clock. This signal is used in synchronous transmission when the

external timing option has been selected. In the external timing mode the

rising edge of EXCLK is used to strobe synchronous DPSK transmit data

applied to on the TXD pin. Also used for serial control interface.

RXCLK

Receive Clock. The falling edge of this clock output is coincident with the

transitions in the serial received data output. The rising edge of RXCLK

can be used to latch the valid output data. RXCLK will be valid as long as

a carrier is present.

RXD

Received Data Output. Serial receive data is available on this pin. The

data is always valid on the rising edge of RXCLK when in synchronous

Weak

Pull-up mode. RXD will output constant marks if no carrier is detected.

TXCLK

Transmit Clock. This signal is used in synchronous transmission to latch

serial input data on the TXD pin. Data must be provided so that valid data

is available on the rising edge of the TXCLK. The transmit clock is derived

from different sources depending upon the synchronization mode

selection. In internal mode the clock is generated internally. In external

mode TXCLK is phase locked to the EXCLK pin. In slave mode TXCLK is

phase locked to the RXCLK pin. TXCLK is always active.

TXD

Transmit Data Input. Serial data for transmission is applied on this pin.

In synchronous modes, the data must be valid on the rising edge of the

TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud) no

clocking is necessary. DPSK data must be 1200/600 bit/s +1%, -2.5%

or +2.3%, -2.5 % in extended over speed mode.

ANALOG INTERFACE AND OSCILLATOR

NAME

TYPE

DESCRIPTION

RXA

Received modulated analog signal input from the telephone line

interface.

TXA1

TXA2

Transmit analog output to the telephone line interface.

XTL1

XTL2

These pins are for the internal crystal oscillator requiring a 11.0592

MHz parallel mode crystal. Load capacitors should be connected from

XTL1 and XTL2 to ground. XTL2 can also be driven from an external

clock.

Off-hook relay driver. This signal is an open drain output capable of

sinking 40 mA and is used for controlling a relay. The output is the

complement of the OH register bit in the ID Register.

1...4 5 678 9 10...26

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与73K224AL相关器件

型号	品牌	描述	获取价格	数据表
73K224BL	TDK	V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid	获取价格
73K224BL	TERIDIAN	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-32IH	TDK	Modem, 2.4kbps Data, PQCC32, PLASTIC, LCC-32	获取价格
73K224BL-IGT	ETC	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-IH	ETC	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-IH/F	TERIDIAN	Single-Chip Modem w/ Integrated Hybrid	获取价格

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