73K224AL

更新时间： 2024-01-01 02:09:47

品牌	Logo	应用领域
东电化 - TDK		调制解调器
页数	文件大小	规格书
26页	274K
描述
V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid

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73K224AL 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	22
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.04	其他特性：	FULL DUPLEX
数据速率：	2.4 Mbps	JESD-30 代码：	R-PDIP-T22
长度：	27.686 mm	功能数量：	1
端子数量：	22	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称供电电压：	5 V
表面贴装：	NO	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

73K224AL 数据手册

73K222BL

V.22, V.21, Bell 212A, Bell 103

Single-Chip Modem with Integrated Hybrid

PIN DESCRIPTION

POWER

NAME

GND

VDD

TYPE

DESCRIPTION

System Ground

Power supply input, 5 V ±10%. Bypass with 0.1 and 22 µF capacitors to

GND.

VREF

ISET

An internally generated reference voltage. Bypass with 0.1 µF capacitor

to ground.

Chip current reference. Sets bias current for op-amps. The chip current is

set by connecting this pin to VDD through a 2 MΩ resistor. ISET should

be bypassed to GND with a 0.1 µF capacitor.

PARALLEL CONTROL INTERFACE

ALE

5-12

Address latch enable. The falling edge of ALE latches the address on

AD0-AD2 and the chip select on CS.

AD0-AD7

I/O

Address/data bus. These bi-directional tri-state multiplexed lines carry

Tristate information to and from the internal registers.

Chip select. A low on this pin during the falling edge of ALE allows a read

cycle or a write cycle to occur. AD0-AD7 will not be driven and no

registers will be written if CS (latched) is not active. The state of CS is

latched on the falling edge of ALE.

CLK

Output clock. This pin is selectable under processor control to be either

the crystal frequency (for use as a processor clock) or 16 times the data

rate for use as a baud rate clock in DPSK modes only. The pin defaults

to the crystal frequency on reset.

INT

Interrupt. This open drain output signal is used to inform the processor

that a detect flag has occurred. The processor must then read the detect

until the processor reads the detect register or does a full reset.

Read. A low requests a read of the 73K222BL internal registers. Data

cannot be output unless both RD and the latched CS are active or low.

I/with

RESET

Reset. An active high signal on this pin will put the chip into an inactive

state. All control register bits (CR0, CR1, Tone) will be reset. The output

of the CLK pin will be set to the crystal frequency. An internal pull-down

resistor permits power-on-reset using a capacitor to VDD.

Pulldown

1 2 3 456 7 8...26

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与73K224AL相关器件

型号	品牌	描述	获取价格	数据表
73K224BL	TDK	V.22, V.21, Bell 212A, Bell 103 Single-Chip Modem with Integrated Hybrid	获取价格
73K224BL	TERIDIAN	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-32IH	TDK	Modem, 2.4kbps Data, PQCC32, PLASTIC, LCC-32	获取价格
73K224BL-IGT	ETC	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-IH	ETC	Single-Chip Modem w/ Integrated Hybrid	获取价格
73K224BL-IH/F	TERIDIAN	Single-Chip Modem w/ Integrated Hybrid	获取价格

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