Datasheet > 72413L45SO

72413L45SO

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	285K
描述
SOIC-20, Tube

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

72413L45SO 数据手册

IDT72413CMOSPARALLELFIFOWITHFLAGS

64 x 5

COMMERCIALTEMPERATURERANGE

OUTPUTREADY(OR)

CONTROLS:

WhenOutputReadyisHIGH,theoutput(Q0-4)containsvaliddata. When

OR is LOW, the FIFO is unavailable for new output data. OR is also used to

cascade many FIFOs together, as shown in Figure 13.

SHIFT IN (SI)

ShiftIncontrolstheinputofthedataintotheFIFO. WhenSIisHIGH, data

canbewrittentotheFIFOviatheD0-4lines. Thedatahastomeetset-upand

holdtimerequirementswithrespecttotherisingedgeofSI.

OUTPUT ENABLE (OE)

OutputEnableisusedtoenabletheFIFOoutputs ontoabus. OEisactive

LOW.

SHIFT OUT (SO)

ShiftOutcontrolstheoutputsdatafromtheFIFO.

ALMOST-FULL/EMPTY FLAG (AF/E)

Almost-Full/EmptyFlagsignalswhentheFIFOis7/8full(56ormorewords)

or 1/8 from empty (8 or less words).

MASTER RESET (MR)

MasterResetclearstheFIFOofanydatastoredwithin. Uponpowerup,the

FIFO should be cleared with a Master Reset. Master Reset is active LOW.

OUTPUTS:

HALF-FULL FLAG (HF)

Half-Full Flag signals when the FIFO has 32 or more words in it.

DATAOUTPUT(Q0-4)

Dataoutputlines, three-state. TheIDT72413hasa5-bitoutput.

INPUT READY (IR)

WhenInputReadyisHIGH,theFIFOisreadyfornewinputdatatobewritten

to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also

used to cascade many FIFOs together, as shown in Figure 13.

1/fIN

tSIH

tSIL

tIRH

tIDS

tIRL

tIDH

INPUT DATA

2748 drw 04

Figure 2. Input Timing

SI⁽⁷⁾

(2)

(4)

(1)

(5)

(3)

(6)

INPUT DATA

STABLE DATA

2748 drw 05

NOTES:

1. IR HIGH indicates space is available and a SI pulse may be applied.

2. Input Data is loaded into the FIFO.

3. IR goes LOW indicating the FIFO is unavailable for new data.

4. The write pointer is incremented.

5. The FIFO is ready for the next word.

6. If the FIFO is full, then IR remains LOW.

7. SI pulses applied while IR is LOW will be ignored (see Figure 4).

Figure 3. The Machanism of Shifting Data Into the FIFO

JUNE 29, 2012

1 2 3 456 7 8...10

下载PDF

与72413L45SO相关器件

型号	品牌	描述	获取价格	数据表
72413L45SOG	IDT	FIFO, 64X5, 19ns, Asynchronous, CMOS, PDSO20, 0.300 INCH, SOIC-20	获取价格
72413-V	MOLEX	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)	获取价格
72414-45	MOLEX	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)	获取价格
72414-45-56	MOLEX	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)	获取价格
72414-49	MOLEX	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)	获取价格
72414-50	MOLEX	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)	获取价格