Datasheet > 72413L45SO

72413L45SO

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	285K
描述
SOIC-20, Tube

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72413L45SO 数据手册

IDT72413CMOSPARALLELFIFOWITHFLAGS

64 x 5

COMMERCIALTEMPERATURERANGE

STANDARD TEST LOAD

DESIGN TEST LOAD

ACTESTCONDITIONS

Input Pulse Levels

GND to 3.0V

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

3ns

1.5V

2K‰

1.5V

TEST POINT

OUTPUT

See Figure 1

2748 tbl 07

30pF*

2748 drw 03

orequivalentcircuit

*Includingscopeandjig

RESISTORVALUESFOR

STANDARDTESTLOAD

IOL

24mA

12mA

8mA

200Ω

390Ω

600Ω

300Ω

760Ω

1200Ω

Figure 1. Output Load

DATAOUTPUT

FUNCTIONALDESCRIPTION:

DataisshiftedoutontheHIGH-to-LOWtransitionofShiftOut(SO).Thiscauses

the internal read pointer to be advanced to the next word location. If data is

present, validdatawillappearontheoutputsandOutputReady(OR)willgo

HIGH.Ifdataisnotpresent,ORwillstayLOWindicatingtheFIFOisempty. The

lastvalidwordreadfromtheFIFOwillremainattheFlFOsoutputwhenitisempty.

WhentheFIFOisnotemptyORgoesLOWontheLOW-to-HlGHtransitionof

SO.

TheIDT72413,65x5FIFOisdesignedusingadual-portRAMarchitecture

asopposedtothetraditionalshiftregisterapproach. ThisFIFOarchitecturehas

awritepointer,areadpointerandcontrollogic,whichallowsimultaneousread

andwriteoperations.Thewritepointerisincrementedbythefallingedgeofthe

ShiftIn(Sl)control;thereadpointerisincrementedbythefallingedgeoftheShift

Out (SO). The Input Ready (IR) signals when the FIFO has an available

memorylocation;OutputReady(OR)signalswhenthereisvaliddataonthe

output. OutputEnable(OE)providesthecapabilityofthree-statingtheFIFO

outputs.

FALL-THROUGHMODE

TheFIFOoperatesinaFall-ThroughModewhendatagetsshiftedintoan

emptyFIFO.Afterthefall-throughdelaythedatapropagatestotheoutput.When

the data reaches the output, the Output Ready (OR) goes HIGH.

AFall-ThroughModealsooccurswhentheFIFOis completelyfull. When

dataisshiftedoutofthefullFIFOalocationisavailablefornewdata. Afterafall-

through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data

canbewrittentotheFIFO. Thefall-throughdelayofaRAM-basedFIFO(one

clockcycle)isfarlessthanthedelayofaShiftregister-basedFIFO.

FIFO RESET

TheFIFOmustberesetuponpowerupusingtheMasterReset(MR)signal.

ThiscausestheFIFOtoenteranemptystatesignifiedbyOutputReady(OR)

beingLOWandInputReady(IR)beingHIGH. Inthisstate, thedataoutputs

(Q0-4) will be LOW.

DATAINPUT

DataisshiftedinontheLOW-to-HIGHtransitionofShiftIn(Sl). Thisloads

inputdataintothefirstwordlocationoftheFIFOandcausesthelnputReady

(IR)togoLOW. OntheHlGH-to-LOWtransitionofSI,thewritepointerismoved

tothenextwordpositionand lRgoesHlGHindicatingthereadinesstoaccept

newdata. IftheFIFOisfull, IRwillremainLOWuntilawordofdataisshifted

out.

SIGNALDESCRIPTIONS:

INPUTS:

DATA INPUT (D0-4)

Data input lines. The IDT72413 has a 5-bit data input.

JUNE 29, 2012

1 2 345 6 7...10

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