Datasheet > 71V416YS15BEGI

71V416YS15BEGI

更新时间： 2023-02-26 16:10:06

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
9页	478K
描述
Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 9 X 9 MM, ROHS COMPLIANT, BGA-48

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71V416YS15BEGI 数据手册

IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 2⁽¹⁾

tRC

ADDRESS

tOH

tAA

(3)

tOHZ

tOE

(3)

tOLZ

(2)

tACS

(3)

tCHZ

tCLZ

BLE

BHE,

(2)

(3)

BHZ

tBLZ

DATAOUT

DATAOUT VALID

6442 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.

3. Transition is measured ±200mV from steady state.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,2,4)

tWC

ADDRESS

tAW

(2)

(5)

tCW

CHZ

tBW

BHE

BLE

tWR

BHZ

tWP

tAS

(5)

tWHZ

(5)

tOW

PREVIOUS DATA VALID ⁽³⁾

DATA VALID

DATAOUT

DATAIN

tDH

DATAIN VALID

6442 drw 0

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as

short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.462

1...3 4 567 8 9

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