Datasheet > 71T75902

71T75902

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
24页	295K
描述
2.5V 1M x 18 ZBT Synchronous 2.5V I/O Flow-through SRAM

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数据手册

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71T75902 数据手册

71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with

2.5V I/O, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5319 tbl 11

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

FunctionalTimingDiagram⁽¹⁾

CYCLE

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

CLOCK

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A18)

CONTROL

(R/W, ADV/LD, BWx)

(2)

DATA

D/Q28

D/Q29

D/Q30

D/Q31

D/Q32

D/Q33

D/Q34

D/Q35

D/Q36

I/O [0:31], I/O P[1:2]

5319 drw 03a

NOTES:

1. This assumes CEN, CE1, CE2 and CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.42

Apr.07.20

1...5 6 789 10 11...24

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