Datasheet > 7133LA55PFI

7133LA55PFI

更新时间： 2023-01-02 23:40:58

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

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7133LA55PFI 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

BUSY

CER

A4R

CEL

BUSYR

A5R

A6R

A4L

10L

A7R

R/WLLB

10R

A9R

(1)

R/WLUB

R/WRLB

IDT7133/43G

GU68-1⁽⁴⁾

GND⁽²⁾

I/O1L

I/O0L

R/WRUB

68-Pin PGA

Top View⁽⁵⁾

I/O3L

I/O2L

I/O14R

I/O15R

I/O5L

I/O4L

I/O13R

I/O12R

I/O7L

I/O8L

I/O6L

I/O10R I/O11R

18 19

I/O8R I/O9R

I/O3R

I/O5R

)

I/O9L

I/O11L

I/O13L

I/O15L GND⁽²I/O1R

I/O0R

I/O2R

(1)

VCC

I/O7R

I/O10L

I/O12L

I/O14L

I/O4R

I/O6R

Pin 1

Designator

2746 drw 04

NOTES:

1. Both VCC pins must be connected to the power supply to ensure reliable operation.

2. Both GND pins must be connected to the ground supply to ensure reliable operation.

3. Package body is approximately 1.18 in x 1.18 in x 0.16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Names

Left Port

Right Port

Names

Chip Enable

CEL

CER

R/W^LUB

R/W^LLB

R/WRUB

R/WRLB

Upper Byte Read/Write Enable

Lower Byte Read/Write Enable

Output Enable

OEL

OER

0L - A10L

0R - A10R

I/O0R - I/O15R

BUSY

Address

I/O^0L- I/O15L

Data Input/Output

Busy Flag

BUSY

VCC

Power

GND

Ground

2746 tbl 01

6.42

1 234 5 6 7...16

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