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71256T36-75 PDF预览

71256T36-75

更新时间： 2022-09-24 16:08:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
24页 234K
描述
256K x 18 Synchronous-Pipelined Cache Tag RAM

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71256T36-75 数据手册

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CY7C1359A/GVT71256T18  
Truth Table[5, 6, 7, 8, 9, 10, 11]  
Address  
Used  
Operation  
CE CE2 CE2 ADSP ADSC  
ADV WRITE OE  
CLK  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Q
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
READ Cycle, Begin Burst  
None  
None  
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None  
L
X
L
L
None  
L
H
H
L
None  
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External  
External  
External  
External  
External  
Next  
L
X
X
L
READ Cycle, Begin Burst  
L
L
L
H
X
L
High-Z  
D
WRITE Cycle, Begin Burst  
READ Cycle, Begin Burst  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst  
L
L
L
H
L
High-Z  
Q
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next  
L
H
L
High-Z  
Q
Next  
L
Next  
L
H
X
X
L
High-Z  
D
Next  
L
Next  
L
L
D
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z  
Q
H
X
X
High-Z  
D
L
D
Partial Truth Table for READ/WRITE[12]  
Function  
READ  
GW  
BWE  
WEH  
WEL  
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
READ  
WRITE one byte  
WRITE all bytes  
L
WRITE all bytes  
X
X
Notes:  
7. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +  
WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW.  
8. WEL enables write to DQ1–DQ9. WEH enables write to DQ10–DQ18.  
9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.  
10. Suspending burst generates wait cycle.  
11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for  
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.  
12. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.  
Document #: 38-05120 Rev. **  
Page 6 of 24  
1...3456789...24

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