CY7C1359A/GVT71256T18
Pin Descriptions
BGA Pins
TQFP Pins
Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
35, 34, 33, 32,
100, 99, 82, 81,
5C, 6C, 2R, 6R, 80,48, 47, 46, 45,
2T, 3T, 5T, 6T
44, 49, 50
5L
3G
93
94
WEL
WEH
Input-
Byte Write Enables: A byte write enable is LOW for a WRITE
Synchronous cycle and HIGH for a READ cycle. WEL controls DQ1–DQ9.
WEH controls DQ10–DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
87
88
BWE
GW
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set-up and hold times around the
rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit
Synchronous WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip en-
Synchronous ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
6B
2B
4F
4G
98
92
97
86
83
CE
CE2
CE2
OE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Synchronous device.
Chip Enable: This active LOW input is used to enable the
input-
Chip Enable: This active HIGH input is used to enable the
Synchronous device.
Input
Output Enable: This activeLOW asynchronousinput enables
the data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control
Synchronous the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes de-
Synchronous vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
7N
6M
52
53
DEN
Input-
Data Input Enable: This active LOW input is used to control
Synchronous the update of data input registers.
MATCH
Output Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
Document #: 38-05120 Rev. **
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