Datasheet > 70V9159L9PFGI

70V9159L9PFGI

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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70V9159L9PFGI 数据手册

NOTE:

A13

s a

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

T70V9159

Description:

Withaninputdataregister,theIDT70V9169/59 hasbeenoptimized

The IDT70V9169/59 is a high-speed 16/8K x 9 bit synchronous

forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An

automaticpowerdownfeature, controlledbyCE0 andCE1, permitsthe

on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using CMOS high-performance technology, these devices

typicallyoperateononly450mWofpower.

Dual-Port RAM. The memory array utilizes Dual-Port memory cells

to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systemstobedesignedwithveryshortcycletimes.

Pin Configurations^(1,2,3,4)

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

A10R

10L

11L

11R

12R

13R

12L

(1)

13L

70V9169/59PF

(5)

Vss

PN100

100-Pin TQFP

(6)

Top View

CE0L

CE0R

CE1R

CNTRST

CE1L

CNTRST

R/W

FT/PIPE

R/W

FT/PIPE

Vss

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5655 drw 02

NOTES:

1. A13 is a NC for IDT70V9159.

2. All VDD pins must be connected to power supply.

3. All VSS pins must be connected to ground supply.

4. Package body is approximately 14mm x 14mm x 1.4mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.422

123 4 5 6 7...16

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