Datasheet > 70V9079L7PFG

70V9079L7PFG

更新时间： 2022-12-29 20:24:56

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	168K
描述
HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

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70V9079L7PFG 数据手册

IDT70V9089/79S/L

High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

CE0R, CE1R

R/W

Names

Chip Enables

CE^0L, CE1L

R/W

Read/Write Enable

Output Enable

Address

(1)

0L - A15L

0R - A15R

I/O0R - I/O7R

CLK

I/O0L - I/O7L

CLK

Data Input/Output

Clock

Address Strobe

Counter Enable

Counter Reset

Flow-Through/Pipeline

Power (3.3V)

Ground (0V)

ADS

CNTEN

CNTRST

FT/PIPE

ADS

CNTEN

CNTRST

FT/PIPE

NOTE:

1. A15X is a NC for IDT70V9079.

2. LB and UB are single buffered regardless of state of FT/PIPE.

3. CEo and CE1 are single buffered when FT/PIPE = VIL,

CEo and CE1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

3750 tbl 01

Truth Table I—Read/Write and

EnableControl^(1,2,3)

Mode

CLK

I/O0-7

High-Z

DATA^IN

↑

Deselected - Power Down

Write

↑

DATA^OUTRead

High-Z Outputs Disabled

3750 tbl 02

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

Truth Table II—Address Counter Control^(1,2,3)

Internal

Address

Internal

Address

Used

External

Address

MODE

CLK

↑

I/O⁽³⁾

DI/O (n) External Address Used

ADS CNTEN CNTRST

L⁽⁴⁾

An + 1

L⁽⁵⁾

I/O(n+1) Counter Enabled—Internal Address generation

↑

An + 1

I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)

L⁽⁴⁾

DI/O(0)

Counter Reset to Address 0

↑

3750 tbl 03

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE⁰and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other signals including CE⁰and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

6.432

1 234 5 6 7...19

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