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70V9079L6PFGI8 PDF预览

70V9079L6PFGI8

更新时间: 2022-12-29 20:24:56
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
19页 168K
描述
HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

70V9079L6PFGI8 数据手册

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IDT70V9089/79S/L  
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)(Cont'd)  
70V9089/79X12  
Com'l & Ind  
70V9089/79X15  
Com'l Only  
Symbol  
Parameter  
Test Condition  
Version  
COM'L  
Typ.(4)  
Max.  
Typ.(4)  
Max.  
Unit  
I
CC  
Dynamic Operating  
Current  
(Both Ports Active)  
S
L
150  
150  
240  
215  
130  
130  
220  
185  
mA  
CE  
L
and CER = VIL  
Outputs Disabled  
(1)  
f = fMAX  
____  
____  
____  
____  
____  
____  
IND  
S
L
150  
215  
I
SB1  
Standby Current  
(Both Ports - TTL  
Level Inputs)  
COM'L  
IND  
S
L
40  
40  
65  
60  
30  
30  
55  
35  
mA  
mA  
CE  
L
and CER = VIH  
(1)  
f = fMAX  
____  
____  
____  
____  
____  
____  
S
L
40  
60  
I
I
I
SB2  
Standby Current  
(One Port - TTL  
Level Inputs)  
COM'L  
S
L
100  
100  
160  
140  
90  
90  
150  
130  
CE"A" = VIL and  
(3)  
CE"B" = VIH  
Active Port Outputs Disabled,  
____  
____  
____  
____  
____  
____  
(1)  
IND  
S
L
f=fMAX  
100  
150  
SB3  
SB4  
Full Standby Current  
(Both Ports -  
CMOS Level Inputs)  
Both Ports CE  
R
and  
mA  
mA  
COM'L  
IND  
S
L
1.0  
0.4  
5
3
1.0  
0.4  
5
3
CE  
L
> VDD - 0.2V  
V
IN > VDD - 0.2V or  
IN < 0.2V, f = 0(2)  
____  
____  
____  
____  
____  
____  
S
L
V
0.4  
3
Full Standby Current  
(One Port -  
CMOS Level Inputs)  
COM'L  
IND  
S
L
90  
90  
150  
130  
80  
80  
140  
120  
CE"A" < 0.2V and  
CE"B" > VDD - 0.2V(5)  
V
IN > VDD - 0.2V or  
____  
____  
____  
____  
____  
____  
S
L
VIN < 0.2V, Active Port  
(1)  
90  
140  
Outputs Disabled, f = fMAX  
3750 tbl 09b  
NOTES:  
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input  
levels of GND to 3V.  
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.  
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).  
5. CEX = VIL means CE0X = VIL and CE1X = VIH  
CEX = VIH means CE0X = VIH or CE1X = VIL  
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V  
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V  
"X" represents "L" for left port or "R" for right port.  
6. 'X' in part number indicates power rating (S or L).  
6
6.42  

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