IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9089/79S
70V9089/79L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.3V, VIN = 0V t
CE
OL = +4mA
OH = -4mA
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
___
___
|
V
o
V
DD
5
5
___
___
|
10
0
= VIH or CE1 = VIL, VOUT = 0V to VDD
V
V
OL
OH
I
0.4
0.4
___
___
Output High Voltage
I
2.4
2.4
V
3750 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l Only
Typ.(4)
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Max.
Typ.(4)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
S
L
220
220
395
350
200
200
335
290
180
180
260
225
mA
CE
L
and CER = VIL
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
70
70
145
130
60
60
115
100
50
50
75
65
mA
mA
CE
L
and CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
S
L
I
I
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
150
150
280
250
130
130
240
210
110
110
170
150
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs Disabled,
____
____
____
____
____
____
____
____
____
____
____
____
(1)
IND
S
L
f=fMAX
SB3
SB4
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
mA
mA
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
CE
L
> VDD - 0.2V
V
V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
____
____
____
____
____
____
____
____
S
L
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
S
L
140
140
270
240
120
120
230
200
100
100
160
140
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
V
V
IN > VDD - 0.2V or
IN < 0.2V, Active Port
____
____
____
____
____
____
____
____
____
____
____
____
S
L
(1)
Outputs Disabled, f = fMAX
3750 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.452
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