IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7519 is a high-speed 256Kx36 (9Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
4Kx36 banks. The device has two independent ports with separate
control,address,andI/Opinsforeachport,allowingeachporttoaccess
any 4Kx36 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
addresspinsundertheuser'sdirectcontrol.
register, the IDT70V7519 has been optimized for applications having
unidirectionalorbidirectionaldataflowinbursts.Anautomaticpowerdown
feature,controlledbyCE0andCE1,permitstheon-chipcircuitryofeach
porttoenteraverylowstandbypowermode.Thedualchipenablesalso
facilitatedepthexpansion.
The70V7519cansupportanoperatingvoltageofeither3.3Vor2.5V
ononeorbothports,controllablebytheOPTpins.Thepowersupplyfor
the core of the device(VDD) remains at 3.3V. Please refer also to the
functionaldescriptiononpage19.
Registersoncontrol,data,andaddressinputsprovideminimalsetup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
PinConfiguration(1,2,3,4)
A1
A2
A3
A6
A7
A8
A9
BE1L
A11
A12
A13
A14
A17
A4
A5
A10
A15
A16
IO19L IO18L
V
SS
BA4L BA0L
A
8L
CLK
L
CNTEN
L
A
4L
A
0L
V
SS
TDO NC
V
DD
OPT
L
I/O17L
B1
B2
B3
B6
BA1L
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
I/O20R
V
SS I/O18R
A
9L
ADS
L
A
5L
A
1L
I/O15R
DDQR I/O16L
TDI BA5L
BE2L
V
SS
V
SS
V
C1
C6
BA2L
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
V
DDQL
I/O19R
V
DDQR PL/FT
L
NC
A
10L BE3L CE1L
V
SS R/W
L
A
6L
3L
A
2L
I/O15L
V
DD I/O16R
V
SS
D1
D2
D6
D9
D11
REPEATL
D3
D5
BA3L
D7
D8
D10
D12
D13
D14 D15
D16
D17
D4
I/O22L
V
SS
A
11L
V
DD
I/O21L
A
7L BE0L
OE
L
A
V
DD I/O17R
V
DDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
V
DDQR I/O21R
I/O12L
VSS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
VDDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
V
SS
G1
G2
G4
G14
G15
G16
G3
G17
I/O26L
V
SS
I/O24R
I/O9L
V
DDQL I/O10L
I/O25L
I/O11R
H3
H4
H1
H2
H16
H17
H14
H15
70V7519BF
BF208(5)
VDDQR I/O25R
V
DD I/O26R
V
SS I/O10R
V
DD IO9R
J1
J2
J3 J4
J14
J15
J16
J17
V
DDQL
V
DD
SS
V
SS
V
SS
V
SS
V
DD
V
SS
V
DDQR
208-Pin fpBGA
Top View(6)
K2
K4
K15
K16
K1
K3
K14
K17
V
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
V
SS
L3
L4
L15
L16
L17
L1
L2
L14
V
DDQR I/O27L
I/O7L
V
SS I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
M14
M15
V
DDQL I/O29L I/O30R
V
SS
I/O5R
V
DDQR
VSS I/O6L
N16
N17
N4
N15
N1
N2
N3
N14
I/O4R I/O5L
I/O30L
V
DDQL
I/O31L
V
SS I/O31R
I/O3R
P1
P2
P3
P4
P5
P7
BA0R
P8
P9
P10
P11
P12
P14
P15
P16
P17
P6
P13
I/O32R I/O32L
V
DDQR I/O35R TRST
A
8R BE1R
V
DD CLK
R
CNTEN
R
I/O2L I/O3L
V
SS I/O4L
BA4R
A
4R
R5
BA5R BA1R
R6
R7
R8
R9
R10
R11
R16
R1 R2
R3
R4
R12
R13
R14
R17
R15
A
9R
BE2R CE0R
VSS ADS
R
I/O1R
V
DDQL
V
SS I/O33L I/O34R TCK
A5R
A
1R
V
SS
DDQR
V
T2
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
BA2R
T7
T10
T11
T12
T13
T14
I/O34L
V
DDQL
TMS NC
I/O33R
BE3R CE1R
I/O0R
V
SS I/O2R
A
10R
V
SS R/W
R
A
6R
A
2R
V
SS
U1
U2
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
DD
U16
U15
V
SS I/O35L PL/FT
R
NC BA3R
A
11R
A
7R
I/O1L
V
DD
OE
R
A
3R
A
0R
V
I/O0L
R
OPT
5618 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2