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70V05S25JGI PDF预览

70V05S25JGI

更新时间: 2024-09-25 00:22:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 162K
描述
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

70V05S25JGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:LCC
包装说明:QCCJ,针数:68
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.27
最长访问时间:25 nsJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.2062 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端子数量:68字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:4.572 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.2062 mm

70V05S25JGI 数据手册

 浏览型号70V05S25JGI的Datasheet PDF文件第2页浏览型号70V05S25JGI的Datasheet PDF文件第3页浏览型号70V05S25JGI的Datasheet PDF文件第4页浏览型号70V05S25JGI的Datasheet PDF文件第5页浏览型号70V05S25JGI的Datasheet PDF文件第6页浏览型号70V05S25JGI的Datasheet PDF文件第7页 
IDT70V05S/L  
HIGH-SPEED 3.3V  
8K x 8 DUAL-PORT  
STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Commercial: 15/20/25/35/55ns (max.)  
Industrial: 20ns (max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT70V05S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V05L  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 68-pin PGA and PLCC, and a 64-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Active:380mW(typ.)  
Standby: 660µW (typ.)  
IDT70V05 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
Green parts available, see ordering information  
Functional Block Diagram  
OEL  
OER  
CE  
L
CE  
R/W  
R
R/W  
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
L
(1,2)  
R
BUSY  
BUSY  
A
12L  
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(2)  
(2)  
INTL  
INTR  
2942 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JUNE 2012  
1
DSC 2941/10  
©2012IntegratedDeviceTechnology,Inc.  

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