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7038L20PFG8 PDF预览

7038L20PFG8

更新时间: 2024-10-02 21:16:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 675K
描述
Dual-Port SRAM, 64KX18, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100

7038L20PFG8 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QFP,Reach Compliance Code:compliant
HTS代码:8542.32.00.41风险等级:5.12
最长访问时间:20 nsJESD-30 代码:S-PQFP-G100
内存密度:1179648 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

7038L20PFG8 数据手册

 浏览型号7038L20PFG8的Datasheet PDF文件第2页浏览型号7038L20PFG8的Datasheet PDF文件第3页浏览型号7038L20PFG8的Datasheet PDF文件第4页浏览型号7038L20PFG8的Datasheet PDF文件第5页浏览型号7038L20PFG8的Datasheet PDF文件第6页浏览型号7038L20PFG8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7038L  
64K x 18 DUAL-PORT  
STATIC RAM  
Features  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
On-chip port arbitration logic  
– Commercial: 15/20ns (max.)  
– Industrial: 20ns (max.)  
Full on-chip hardware support of semaphore signaling  
between ports  
Low-power operation  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
TTL-compatible, single 5V (±10%) power supply  
Available in a 100-pin TQFP  
– IDT7038L  
Active: 1W (typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
IDT7038 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
Green parts available, see ordering information  
FunctionalBlockDiagram  
R/  
WL  
R/WR  
UBL  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LBR  
LB  
I/O 9-17L  
I/O 0-8L  
I/O9-17R  
I/O0-8R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSY  
R
BUSY  
L
.
64Kx18  
MEMORY  
ARRAY  
7038  
15L  
A
15R  
0R  
A
Address  
Decoder  
Address  
Decoder  
A
0L  
A
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
CE1R  
OEL  
OER  
R/W  
L
R/WR  
SEM  
L
L
SEM  
R
(2)  
(2)  
INTR  
INT  
M/S(1)  
4837 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
FEBRUARY 2015  
1
DSC-4837/5  
©2015 Integrated Device Technology, Inc.  

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