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650R-07LFT PDF预览

650R-07LFT

更新时间: 2024-11-27 01:06:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
9页 215K
描述
NETWORKING CLOCK SOURCE

650R-07LFT 数据手册

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DATASHEET  
NETWORKING CLOCK SOURCE  
ICS650-07C  
Description  
Features  
The ICS650-07C is a low cost, low jitter, high performance  
clock synthesizer for networking applications. Using analog  
Phase-Locked Loop (PLL) techniques, the device accepts a  
12.5 MHz or 25.00 MHz clock or fundamental mode crystal  
input to produce multiple output clocks for networking chips,  
PCI devices, SDRAM, and ASICs. The ICS650-07C outputs  
all have 0 ppm synthesis error.  
Packaged in 20-pin tiny SSOP (QSOP)  
Pb (lead) free package  
12.5 MHz or 25.00 MHz fundamental crystal or clock  
input  
Six output clocks with selectable frequencies  
SDRAM frequencies of 67, 83, 100, and 133 MHz  
Buffered crystal reference output  
See the MK74CB214, ICS551, and ICS552-01 for non-PLL  
buffer devices which produce multiple low-skew copies of  
these output clocks.  
Zero ppm synthesis error in all clocks  
Ideal for PMC-Sierra’s ATM switch chips  
See the ICS570, ICS9112-16/17/18 for zero delay buffers  
that can synchronize outputs and other needed clocks.  
Full CMOS output swing with 25 mA output drive  
capability at TTL levels  
Advanced, low power, sub-micron CMOS process  
3.0 V to 5.5 V operating voltage  
Block Diagram  
VDD  
2
CLKA1  
CLKA2  
CLKB1  
/2  
/2  
2
ACS1, 0  
Clock  
2
Synthesis  
and Control  
Circuitry  
BCS1, 0  
CLKB2  
CCS  
CLKC1  
CLKC2  
12.5 MHz or 25.00 MHz  
Crystal or Clock  
Clock  
Buffer/  
Crystal  
Oscillator  
X1/ICLK  
REFOUT  
X2  
2
Optional crystal capacitors are shown and  
may be required for tuning of initial accuracy  
OE (all outputs)  
GND  
IDT™ / ICS™ NETWORKING CLOCK SOURCE  
1
ICS650-07C  
REV D 102709  

650R-07LFT 替代型号

型号 品牌 替代类型 描述 数据表
650R-07LF IDT

完全替代

NETWORKING CLOCK SOURCE
650R-07ILFT IDT

完全替代

NETWORKING CLOCK SOURCE
650R-07ILF IDT

完全替代

NETWORKING CLOCK SOURCE

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