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5V49EE904NLGI

更新时间： 2024-01-27 02:50:05

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器微控制器和处理器 PC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
29页	652K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

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技术参数
数据手册

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5V49EE904NLGI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	VFQFPN
包装说明：	,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	8.54
Samacsys Confidence：	3	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/11129684.2.1.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=11129684
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=11129684	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=11129684
Samacsys PartID：	11129684	Samacsys Image：	https://componentsearchengine.com/Images/9/5V49EE904NLGI.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/2/5V49EE904NLGI.jpg	Samacsys Pin Count：	33
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	NLG 32 P1*	Samacsys Released Date：	2020-01-23 04:01:50
Is Samacsys：	N	JESD-609代码：	e3
湿度敏感等级：	3	端子面层：	Matte Tin (Sn) - annealed
Base Number Matches：	1

5V49EE904NLGI 数据手册

IDT5V49EE904

EEPROM PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

internal load capacitance is set.

XTAL load cap = 3.5 pF + XTAL[4:0] * 0.125 pF (Eq. 1)

Reference Clock Input Pins and

Selection

The IDT5V49EE904 supports up to two clock inputs. One of

the clock inputs (XIN/ REF) can be driven by either an

external crystal or a reference clock. The second clock input

(CLKIN) can only be driven from an external reference

clock. The CLKSEL pin selects the input clock from either

XTAL/REF or CLKIN.

Parameter

Bits

Step (pF)

Min (pF)

Max (pF)

XTAL

0.125

When using an external reference clock instead of a crystal

on the XTAL/REF pin, the input load capacitors may be

completely bypassed. This allows for the input frequency to

be up to 200 MHz. When using an external reference clock,

the XOUT pin must be left floating, XTAL must be

programmed to the default value of “00h”, and the crystal

drive strength bit, XDRV (0x06), must be set to the default

value of “11h”.

Either clock input can be set as the primary clock. The

primary clock designation is to establish which is the main

reference clock to the PLLs. The non-primary clock is

designated as the secondary clock in case the primary clock

goes absent and a backup is needed. The PRIMSRC bit

(0xBE through 0xC3) determines which clock input will be

selected as primary clock. When PRIMSRC bit is "0",

XIN/REF is selected as the primary clock, and when "1",

CLKIN as the primary clock.

Switchover Modes

The IDT5V49EE904 features redundant clock inputs which

supports both Automatic and Manual switchover mode.

These two modes are determined by the configuration bits,

SM (0xBE through 0xC3). The primary clock source can be

programmed, via the PRIMSRC bit, to be either XIN/REF or

CLKIN. The other clock input will be considered as the

secondary source. Note that the switchover modes are

asynchronous. If the reference clocks are directly routed to

OUTx with no phase relationship, short pulses can be

generated during switchover. The automatic switchover

mode will work only when the primary clock source is

XIN/REF. Switchover modes are not supported for crystal

input configurations.

The two external reference clocks can be manually selected

using the CLKSEL pin. The SM bits (0xBE through 0xC3)

must be set to "0x" for manual switchover which is detailed

in SWITCHOVER MODES section.

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

When the XIN/REF pin is driven by a crystal, it is important

to set the internal inverter oscillator drive strength and

tuning/load capacitor values correctly to achieve the best

clock performance. These values are programmable

Manual Switchover Mode

When SM[1:0] is "0x", the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to

switch between the primary and secondary clock sources.

As previously mentioned, the primary and secondary clock

source setting is determined by the PRIMSRC bit. During

the switchover, no glitches will occur at the output of the

device, although there may be frequency and phase drift,

depending on the exact phase and frequency relationship

between the primary and secondary clocks.

through I C interface to allow for maximum compatibility

with crystals from various manufacturers, processes,

performances, and qualities. The internal load capacitors

are true parallel-plate capacitors for ultra-linear

performance. Parallel-plate capacitors were chosen to

reduce the frequency shift that occurs when non-linear load

capacitance interacts with load, bias, supply, and

temperature changes. External non-linear crystal load

capacitors should not be used for applications that are

sensitive to absolute frequency requirements. The value of

the internal load capacitors are determined by XTAL[4:0]

bits. The load capacitance can be set with a resolution of

0.125 pF for a total crystal load ranging from 3.5 pF to 7.5

pF. Check with the crystal vendor's load capacitance

specification for the exact setting to tune the internal load

capacitor. The following equation governs how the total

Automatic Switchover Mode

The redundant inputs are in automatic switchover mode.

Automatic switchover mode has revertive functionality. The

input clock selection will switch to the secondary clock

source when there are no transitions on the primary clock

source for two secondary clock cycles. If both reference

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE904 REV H 022310

1...3 4 567 8 9...29

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