Datasheet > 5V60002DCG8

5V60002DCG8

更新时间： 2024-01-20 05:33:17

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
7页	170K
描述
PLL Based Clock Driver, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8

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技术参数
数据手册

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5V60002DCG8 技术参数

生命周期：	Active	零件包装代码：	SOIC
包装说明：	,	针数：	8
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.77	JESD-30 代码：	R-PDSO-G8
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	端子数量：	8
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	端子形式：	GULL WING
端子位置：	DUAL	Base Number Matches：	1

5V60002DCG8 数据手册

PRELIMINARY DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER

IDT5V60002

Description

Features

The IDT5V60002 is a high speed, high output drive, low

phase noise Zero Delay Buffer (ZDB) which integrates IDT’s

proprietary analog/digital Phase Locked Loop (PLL)

techniques. The IDT5V60002, part of IDT’s ClockBlocks™

family, was designed to operate at higher frequencies, with

faster rise and fall times, and with lower phase noise. The

zero delay feature means that the rising edge of the input

clock aligns with the rising edges of both outputs, giving the

appearance of no delay through the device. There are two

outputs on the chip, one being a low-skew divide by two of

the other.

• Packaged in 8-pin SOIC (RoHS compliant)

• Can function as low phase noise x2 multiplier

• Low skew outputs. One is ÷2 of other

• Input clock frequency up to 160 MHz at 3.3 V

• Phase noise of better than -100 dBc/Hz from 1 kHz to 1

MHz offset from carrier

• Can recover poor input clock duty cycle

• Output clock duty cycle of 45/55 at 3.3 V

• High drive strength for >100 MHz outputs

The chip is ideal for synchronizing outputs in a large variety

of systems, from personal computers to data

• Full CMOS clock swings with 25 mA drive capability at

TTL levels

communications to video. By allowing offchip feedback

paths, the IDT5V60002 can eliminate the delay through

other devices. The use of dividers in the feedback path will

enable the part to multiply by more than two.

• Advanced, low power CMOS process

• Operating voltage of 3.0

Block Diagram

IDT™ LOW PHASE NOISE ZERO DELAY BUFFER

IDT5V60002

REV A 010307

12 3 4 5 6 7

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