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5V49EE902NLGI PDF预览

5V49EE902NLGI

更新时间: 2024-02-03 06:47:28
品牌 Logo 应用领域
艾迪悌 - IDT 可编程只读存储器电动程控只读存储器电可擦编程只读存储器驱动逻辑集成电路
页数 文件大小 规格书
33页 372K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

5V49EE902NLGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:VFQFPN
包装说明:VFQFPN-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:3.52
Samacsys Description:VFQFP-N 5 X 5 NO LEAD系列:5V
输入调节:MUXJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:7
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.075 ns
座面最大高度:0.9 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
最小 fmax:500 MHz

5V49EE902NLGI 数据手册

 浏览型号5V49EE902NLGI的Datasheet PDF文件第24页浏览型号5V49EE902NLGI的Datasheet PDF文件第25页浏览型号5V49EE902NLGI的Datasheet PDF文件第26页浏览型号5V49EE902NLGI的Datasheet PDF文件第28页浏览型号5V49EE902NLGI的Datasheet PDF文件第29页浏览型号5V49EE902NLGI的Datasheet PDF文件第30页 
IDT5V49EE902  
EEPROM PROGRAMMABLE CLOCK GENERATOR  
CLOCK SYNTHESIZER  
Default  
Bit #  
Register  
Addr  
Description  
Hex  
Value  
00  
7
6
5
4
3
2
1
0
SLEW2[1:0]  
CMEN3  
CMEN1  
0x77  
CMEN# - common mode enable  
Set to 1 for LVDS, LVPECL  
Set to 0 for LVTTL  
OEM3[1:0]  
OEM4[1:0]  
SLEW3[1:0]  
SLEW4[1:0]  
INV3[1:0]  
INV4[1:0]  
LVL3[1:0]  
0x78  
0x79  
00  
00  
OEM3 controls OUT3 and OUT6  
LVL4[1:0]  
OEM4 controls OUT4 and  
OUT4b  
OEM5[1:0]  
SLEW5[1:0]  
SLEW6[1:0]  
INV5[1:0]  
LVL5[1:0]  
0x7A  
00  
00  
OEM5 controls OUT5 and  
OUT5b  
CMEN5  
CMEN4  
0x7B  
0x7C  
0x7D  
0x7E  
0x7F  
0x80  
0x81  
0x82  
0x83  
0x84  
0x85  
0x86  
0x87  
0x88  
0x89  
0x8A  
0x8B  
0x8C  
0x8D  
0x8E  
0x8F  
0x90  
0x91  
0x92  
0x93  
0x94  
0x95  
0x96  
0x97  
0x98  
0x99  
0x9A  
0x9B  
0x9C  
0x9D  
0x9E  
0x9F  
0xA0  
0xA1  
0xA2  
0xA3  
0xA4  
0xA5  
0xA6  
1
Reserved  
Reserved  
Reserved  
Reserved  
XX  
1
XX  
1
XX  
1
XX  
SSVCO[15:8]_CFG0  
SSVCO[15:8]_CFG1  
SSVCO[15:8]_CFG2  
SSVCO[15:8]_CFG3  
SSVCO[15:8]_CFG4  
SSVCO[15:8]_CFG5  
Reserved  
00  
00  
00  
00  
00  
00  
00  
00  
FF  
FF  
FF  
FF  
FF  
FF  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
7F  
PLL3 Spread Spectrum  
Feedback Counter  
Reserved  
Reserved  
Reserved  
PM1_CFG0  
PM1_CFG1  
PM1_CFG2  
PM1_CFG3  
PM1_CFG4  
PM1_CFG5  
PM2_CFG4  
PM2_CFG5  
PM2_CFG0  
PM2_CFG1  
PM2_CFG2  
PM2_CFG3  
PM3_CFG0  
PM3_CFG1  
PM3_CFG2  
PM3_CFG3  
PM3_CFG4  
PM3_CFG5  
PM4_CFG4  
PM4_CFG5  
PM4_CFG0  
PM4_CFG1  
PM4_CFG2  
PM4_CFG3  
PM5_CFG0  
PM5_CFG1  
PM5_CFG2  
PM5_CFG3  
PM5_CFG4  
PM5_CFG5  
PM6_CFG4  
Q1[6:0]_CFG0  
Output Divides  
for Q<>111111,  
PM=0 - Divide by 2  
PM=1, (Q+2)*2  
for Q=1111111  
PM=0, disable the output divider  
PM=1, bypass the output divide,  
(divide by 1)  
Q1[6:0]_CFG1  
Q1[6:0]_CFG2  
Q1[6:0]_CFG3  
Q1[6:0]_CFG4  
Q1[6:0]_CFG5  
Q2[6:0]_CFG4  
Q2[6:0]_CFG5  
Q2[6:0]_CFG0  
Q2[6:0]_CFG1  
Q2[6:0]_CFG2  
Q2[6:0]_CFG3  
Q3[6:0]_CFG0  
Q3[6:0]_CFG1  
Q3[6:0]_CFG2  
Q3[6:0]_CFG3  
Q3[6:0]_CFG4  
Q3[6:0]_CFG5  
Q4[6:0]_CFG4  
Q4[6:0]_CFG5  
Q4[6:0]_CFG0  
Q4[6:0]_CFG1  
Q4[6:0]_CFG2  
Q4[6:0]_CFG3  
Q5[6:0]_CFG0  
Q5[6:0]_CFG1  
Q5[6:0]_CFG2  
Q5[6:0]_CFG3  
Q5[6:0]_CFG4  
Q5[6:0]_CFG5  
Q6[6:0]_CFG4  
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR  
27  
IDT5V49EE902 REV Q 071015  

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