Datasheet > 5M240ZT100I5

5M240ZT100I5

更新时间： 2024-02-06 14:06:57

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟可编程逻辑
页数	文件大小	规格书
166页	3966K
描述
Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100

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5M240ZT100I5 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TFQFP, TQFP100,.63SQ	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	0.98	Samacsys Confidence：	3
Samacsys Status：	Released	2D Presentation：	https://componentsearchengine.com/2D/0T/1376791.1.2.png
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=1376791	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=1376791
3D View：	https://componentsearchengine.com/viewer/3D.php?partID=1376791	Samacsys PartID：	1376791
Samacsys Image：	https://componentsearchengine.com/Images/9/5M240ZT100I5N.jpg	Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/5M240ZT100I5N.jpg
Samacsys Pin Count：	100	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Quad Flat Packages	Samacsys Footprint Name：	100-Pin TQFP
Samacsys Released Date：	2018-10-22 08:47:48	Is Samacsys：	N
其他特性：	YES	最大时钟频率：	118.3 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e3	JTAG BST：	YES
长度：	14 mm	I/O 线路数量：	79
宏单元数：	192	端子数量：	100
最高工作温度：	100 °C	最低工作温度：	-40 °C
组织：	79 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP100,.63SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.8,1.2/3.3 V	可编程逻辑类型：	FLASH PLD
传播延迟：	14 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Programmable Logic Devices
最大供电电压：	1.89 V	最小供电电压：	1.71 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

5M240ZT100I5 数据手册

1. MAX V Device Family Overview

MV51001-1.2

The MAX^®V family of low cost and low power CPLDs offer more density and I/Os

per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements

(LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide

programmable solutions for applications such as I/O expansion, bus and protocol

bridging, power monitoring and control, FPGA configuration, and analog IC

interface.

MAX V devices feature on-chip flash storage, internal oscillator, and memory

functionality. With up to 50% lower total power versus other CPLDs and requiring as

few as one power supply, MAX V CPLDs can help you meet your low power design

requirement.

This chapter contains the following sections:

■

“Feature Summary” on page 1–1

“Integrated Software Platform” on page 1–3

“Device Pin-Outs” on page 1–3

“Ordering Information” on page 1–4

Feature Summary

The following list summarizes the MAX V device family features:

■

Low-cost, low-power, and non-volatile CPLD architecture

Instant-on (0.5 ms or less) configuration time

Standby current as low as 25 µA and fast power-down/reset operation

Fast propagation delay and clock-to-output times

Internal oscillator

Emulated RSDS output support with a data rate of up to 200 Mbps

Emulated LVDS output support with a data rate of up to 304 Mbps

Four global clocks with two clocks available per logic array block (LAB)

User flash memory block up to 8 Kbits for non-volatile storage with up to 1000

read/write cycles

■

Single 1.8-V external supply for device core

MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■

Schmitt triggers enabling noise tolerant inputs (programmable per pin)

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

May 2011

1...6 7 8910 11 12...166

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与5M240ZT100I5相关器件

型号	品牌	描述	获取价格	数据表
5M240ZT144A5N	INTEL	Flash PLD, 17.7ns, 192-Cell, CMOS, PQFP144	获取价格
5M240ZT144C4	ALTERA	Flash PLD, 9.5ns, PQFP144, 22 X 22 MM, 0.50 MM PITCH, TQFP-144	获取价格
5M240ZT144C4N	ALTERA	Flash PLD, 9.5ns, 192-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144	获取价格
5M240ZT144I5N	ALTERA	Flash PLD, 17.7ns, 192-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144	获取价格
5M240ZT64A4N	ALTERA	MAX V Device Handbook	获取价格
5M240ZT64A5N	ALTERA	MAX V Device Handbook	获取价格

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