Datasheet > 5CSEMA6F31C8N

5CSEMA6F31C8N

更新时间： 2024-02-13 04:17:45

品牌	Logo	应用领域
英特尔 - INTEL		栅可编程逻辑
页数	文件大小	规格书
66页	1360K
描述
Field Programmable Gate Array, 110000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5CSEMA6F31C8N 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA896,30X30,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	2.06
JESD-30 代码：	S-PBGA-B896	JESD-609代码：	e1
长度：	31 mm	湿度敏感等级：	3
输入次数：	288	逻辑单元数量：	110000
输出次数：	288	端子数量：	896
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA896,30X30,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.1,1.2/3.3,2.5 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	2 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.13 V
最小供电电压：	1.07 V	标称供电电压：	1.1 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	31 mm	Base Number Matches：	1

5CSEMA6F31C8N 数据手册

Electrical Characteristics

Page 5

Table 3. Recommended Operating Conditions for Cyclone V Devices (Part 2 of 2)

Minimum

Maximum

Symbol

Description

Power supply ramp time

Condition

Typical

Unit

(5)

Standard POR

Fast POR

200 µs

—

100 ms

4 ms

—

(4)

t_RAMP

Notes to Table 3:

(1) V_CCPDmust be 2.5 V when V_CCIOis 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. V_CCPDmust be 3.0 V when V_CCIOis 3.0 V. V_CCPDmust be 3.3 V when V_CCIO

is 3.3 V.

(2) PLL digital voltage is regulated from V_{CCA_FPLL}

(3) If you do not use the design security feature in Cyclone V devices, connect V_CCBATto a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset

(POR) circuitry monitors V_CCBAT. Cyclone V devices do not exit POR if V_CCBATis not powered up.

(4) This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMPspecifications for standard POR when HPS_PORSEL = 0 and

t_RAMPspecifications for fast POR when HPS_PORSEL = 1.

(5) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance

requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

Table 4 lists the transceiver power supply recommended operating conditions for

Cyclone V GX, GT, SX, and ST devices.

Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices

Symbol

V_{CCH_GXBL}

Description

Minimum ⁽³⁾

2.375

Typical

2.5

Maximum ⁽³⁾Unit

Transceiver high voltage power (left side)

Transmitter and receiver power (left side)

Clock network power (left side)

2.625

(1), (2)

V_{CCE_GXBL}

V_{CCL_GXBL}

1.07/1.17

1.1/1.2

1.13/1.23

(1), (2)

Notes to Table 4:

(1) Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full

compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in

Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.

(2) Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter

specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT devices only). For more information about the

maximum full duplex channels recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations

in Cyclone V Devices chapter.

(3) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to

the PDN tool for the additional budget for the dynamic tolerance requirements.

Table 5 lists the steady-state voltage values expected from Cyclone V

system-on-a-chip (SoC) devices with ARM^®-based hard processor system (HPS).

Power supply ramps must all be strictly monotonic, without plateaus.

Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices ⁽¹⁾(Part 1 of 2)

Symbol

V_{CC_HPS}

Description

Minimum ⁽⁴⁾

Typical

Maximum ⁽⁴⁾Unit

HPS core voltage and periphery circuitry power

supply

1.07

1.1

1.13

HPS I/O pre-driver (3.3 V) power supply

HPS I/O pre-driver (3.0 V) power supply

HPS I/O pre-driver (2.5 V) power supply

3.135

2.85

3.3

3.0

2.5

3.465

3.15

(2)

V_{CCPD_HPS}

2.375

2.625

July 2014 Altera Corporation

Cyclone V Device Datasheet

1 2 3 456 7 8...66

下载PDF

与5CSEMA6F31C8N相关器件

型号	品牌	描述	获取价格	数据表
5CSEMA6U23I7N	INTEL	Field Programmable Gate Array, 110000-Cell, CMOS, PBGA672, ROHS COMPLIANT, UBGA-672	获取价格
5CSTD5	ALTERA	Cyclone V Device Handbook	获取价格
5CSTD6	ALTERA	Cyclone V Device Handbook	获取价格
5CSTFD5D5F31I7N	INTEL	Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896	获取价格
5CSTFD6D5F31I7N	INTEL	Field Programmable Gate Array, 110000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896	获取价格
5CSXC4	ALTERA	Cyclone V Device Handbook	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

5CSEMA6F31C8N

5CSEMA6F31C8N 技术参数

5CSEMA6F31C8N 数据手册

与5CSEMA6F31C8N相关器件

与5CSEMA6F31C8N相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

5CSEMA6F31C8N

5CSEMA6F31C8N 技术参数

5CSEMA6F31C8N 数据手册

与5CSEMA6F31C8N相关器件

与5CSEMA6F31C8N相关文章

您还可以找

您在本页遇到什么问题？