Datasheet > 5CEFA7F31C6N

5CEFA7F31C6N

更新时间： 2024-01-23 19:37:36

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
95页	1359K
描述
Field Programmable Gate Array, 149500-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

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5CEFA7F31C6N 数据手册

CV-51002

2015.12.04

Document Revision History

Date

Version

Changes

March 2013

3.2

•

Added HPS reset information in the “HPS Specifications” section.

Added Table 57.

Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.

Updated Figure 18.

January 2013

3.1

3.0

Updated Table 4, Table 20, and Table 56.

November 2012

•

Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table

28, Table 52, Table 55, Table 56, and Table 59.

•

Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.

Added HPS information:

•

Added “HPS Specifications” section.

Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42,

Table 43, Table 44, Table 45, and Table 46.

•

Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,

Figure 14, Figure 15, and Figure 16.

Updated Table 3.

June 2012

2.0

Updated for the Quartus II software v12.0 release:

•

Restructured document.

Removed “Power Consumption” section.

Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34,

Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46.

Added Table 22, Table 23, and Table 29.

Added Figure 1 and Figure 2.

Added “Initialization” and “Configuration Files” sections.

•

Cyclone V Device Datasheet

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