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5962F9683101VPA PDF预览

5962F9683101VPA

更新时间: 2024-02-21 23:56:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 放大器
页数 文件大小 规格书
9页 109K
描述
Radiation Hardened, Dual, High Speed Low Power, Video Closed Loop Buffer

5962F9683101VPA 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.56
放大器类型:BUFFER标称带宽 (3dB):340 MHz
JESD-30 代码:R-GDIP-T8标称负供电电压 (Vsup):-5 V
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.08 mm
标称压摆率:1155 V/us标称供电电压 (Vsup):5 V
表面贴装:NO技术:BIPOLAR
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
总剂量:300k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

5962F9683101VPA 数据手册

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HS-1212RH  
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS  
APPROACH  
PEAKING (dB)  
BW (MHz)  
430  
±0.1dB GAIN FLATNESS (MHz)  
Remove -IN Pin  
+R = 620Ω  
4.5  
0
21  
27  
15  
70  
40  
220  
S
+R = 620and Remove -IN Pin  
0.5  
0.6  
0.7  
215  
S
Short +IN to -IN (e.g., Pins 2 and 3)  
100pF Capacitor Between +IN and -IN  
280  
290  
Terminated microstrip signal lines are recommended at the  
input and output of the device. Capacitance directly on the  
output must be minimized, or isolated as discussed in the  
next section.  
Evaluation Board  
The performance of the HS-1212RH may be evaluated using  
the HA5023 Evaluation Board, slightly modified as follows:  
1. Remove the two feedback resistors, and leave the  
connections open.  
An example of a good high frequency layout is the  
Evaluation Board shown in Figure 3.  
2. a. For A = +1 evaluation, remove the gain setting  
V
resistors (R ), and leave pins 2 and 6 floating.  
1
Driving Capacitive Loads  
b. For A = +2, replace the gain setting resistors (R )  
V
1
Capacitive loads, such as an A/D input, or an improperly  
terminated transmission line will degrade the amplifier’s  
phase margin resulting in frequency response peaking and  
possible oscillations. In most cases, the oscillation can be  
with 0resistors to GND.  
The modified schematic for amplifier 1, and the board layout  
are shown in Figures 2 and 3.  
To order evaluation boards (part number HA5023EVAL),  
please contact your local sales office.  
avoided by placing a resistor (R ) in series with the output  
S
prior to the capacitance.  
Figure 1 details starting points for the selection of this  
resistor. The points on the curve indicate the R and C  
combinations for the optimum bandwidth, stability, and  
S
L
50Ω  
OUT  
1
2
3
4
8
7
6
5
+5V  
10µF  
settling time, but experimental fine tuning is recommended.  
Picking a point above or to the right of the curve yields an  
overdamped response, while points below or left of the curve  
indicate areas of underdamped performance.  
R
(NOTE)  
1
0.1µF  
+
IN  
50Ω  
GND  
GND  
R
and C form a low pass network at the output, thus  
L
S
5V  
10µF  
limiting system bandwidth well below the amplifier bandwidth  
(A = +1)  
V
NOTE: R  
=
1
OR 0(A = +2)  
0.1µF  
V
of 350MHz. By decreasing R as C increases (as  
S
L
illustrated in the curves), the maximum bandwidth is  
obtained without sacrificing stability. In spite of this,  
bandwidth decreases as the load capacitance increases.  
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC  
50  
40  
30  
20  
A
= +1  
V
A
= +2  
150  
V
10  
0
0
100  
200  
300  
400  
50  
250  
350  
LOAD CAPACITANCE (pF)  
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD  
CAPACITANCE  
3

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