HS-1212RH
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
PEAKING (dB)
BW (MHz)
430
±0.1dB GAIN FLATNESS (MHz)
Remove -IN Pin
+R = 620Ω
4.5
0
21
27
15
70
40
220
S
+R = 620Ω and Remove -IN Pin
0.5
0.6
0.7
215
S
Short +IN to -IN (e.g., Pins 2 and 3)
100pF Capacitor Between +IN and -IN
280
290
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Evaluation Board
The performance of the HS-1212RH may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the
connections open.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
2. a. For A = +1 evaluation, remove the gain setting
V
resistors (R ), and leave pins 2 and 6 floating.
1
Driving Capacitive Loads
b. For A = +2, replace the gain setting resistors (R )
V
1
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
with 0Ω resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
avoided by placing a resistor (R ) in series with the output
S
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R and C
combinations for the optimum bandwidth, stability, and
S
L
50Ω
OUT
1
2
3
4
8
7
6
5
+5V
10µF
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
R
(NOTE)
1
0.1µF
−
+
IN
50Ω
GND
GND
R
and C form a low pass network at the output, thus
L
S
−5V
10µF
limiting system bandwidth well below the amplifier bandwidth
∞ (A = +1)
V
NOTE: R
=
1
OR 0Ω (A = +2)
0.1µF
V
of 350MHz. By decreasing R as C increases (as
S
L
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth decreases as the load capacitance increases.
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
50
40
30
20
A
= +1
V
A
= +2
150
V
10
0
0
100
200
300
400
50
250
350
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
3