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5962F9583402VXA PDF预览

5962F9583402VXA

更新时间: 2024-02-28 20:05:19
品牌 Logo 应用领域
艾法斯 - AEROFLEX 接口集成电路接收机
页数 文件大小 规格书
11页 81K
描述
Quad Receiver

5962F9583402VXA 技术参数

生命周期:Obsolete包装说明:DFP,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644; IEEE 1596.3
功能数量:4最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装形式:FLATPACK
认证状态:Not Qualified最大接收延迟:8 ns
接收器位数:4筛选级别:MIL-PRF-38535 Class V
座面最大高度:2.921 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
总剂量:300k Rad(Si) V宽度:6.731 mm
Base Number Matches:1

5962F9583402VXA 数据手册

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Receiver Fail-Safe  
2. Terminated Input. If the driver is disconnected (cable  
unplugged), or if the driver is in a three-state condition,  
the receiver output will again be in a HIGH state, even  
with the end of cable 100W termination resistor across  
the input pins. The unplugged cable can become a  
floating antenna which can pick up noise. If the cable  
picks up more than 10mV of differential noise, the  
receiver may see the noise as a valid signal and switch.  
To insure that any noise is seen as common-mode and  
not differential, a balanced interconnect should be used.  
Twisted pair cable offers better balance than flat ribbon  
cable.  
The UT54LVDS032 receiver is a high gain, high speed device  
that amplifies a small differential signal (20mV) toTTL logic  
levels. Due to the high gain and tight threshold of the receiver,  
care should be taken to prevent noise from appearing as a valid  
signal.  
The receiver’s internal fail-safe circuitry is designed to source/  
sink a small amount of current, providing fail-safe protection (a  
stable known state of HIGH output voltage) for floating,  
terminated or shorted receiver inputs.  
1. Open Input Pins. The UT54LVDS032 is a quad  
receiver device, and if an application requires only 1, 2  
or 3 receivers, the unused channel(s) inputs should be  
left OPEN. Do not tie unused receiver inputs to ground  
or any other voltages. The input is biased by internal high  
value pull up and pull down resistors to set the output to  
a HIGH state. This internal circuitry will guarantee a  
HIGH, stable output state for open inputs.  
3. Shorted Inputs. If a fault condition occurs that shorts  
the receiver inputs together, thus resulting in a 0V  
differential input voltage, the receiver output remains in  
a HIGH state. Shorted input fail-safe is not supported  
across the common-mode range of the device (VSS to  
2.4V). It is only supported with inputs shorted and no  
external common-mode voltage applied.  
3

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