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5962-9952001QYA

更新时间： 2024-02-14 11:48:08

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		可编程逻辑输入元件时钟
页数	文件大小	规格书
64页	1733K
描述
5V, 3.3V, ISRTM High-Performance CPLDs

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5962-9952001QYA 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.83
Is Samacsys：	N	最大时钟频率：	80 MHz
JESD-609代码：	e0	长度：	16.4846 mm
专用输入次数：	1	I/O 线路数量：	37
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	1 DEDICATED INPUTS, 37 I/O	输出函数：	MACROCELL
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	EE PLD	传播延迟：	12 ns
认证状态：	Qualified	筛选级别：	MIL-PRF-38535 Class Q
座面最大高度：	4.826 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	16.4846 mm	Base Number Matches：	1

5962-9952001QYA 数据手册

Ultra37000 CPLD Family

Speed Bins

Device

200

167

154

143

125

100

CY37032V

CY37064V

CY37128V

CY37192V

CY37256V

CY37384V

CY37512V

Device-Package Offering and I/O Count

Device

CY37032V

CY37064V

CY37128V

CY37192V

CY37256V

CY37384V

CY37512V

133

125

133

165

197

165

269

Logic Block

Architecture Overview of Ultra37000 Family

The logic block is the basic building block of the Ultra37000

architecture. It consists of a product term array, an intelligent

product-term allocator, 16 macrocells, and a number of I/O

cells. The number of I/O cells varies depending on the device

used. Refer to Figure 1 for the block diagram.

Programmable Interconnect Matrix

The PIM consists of a completely global routing matrix for

signals from I/O pins and feedbacks from the logic blocks. The

PIM provides extremely robust interconnection to avoid fitting

and density limitations.

Product Term Array

The inputs to the PIM consist of all I/O and dedicated input pins

and all macrocell feedbacks from within the logic blocks. The

number of PIM inputs increases with pin count and the number

of logic blocks. The outputs from the PIM are signals routed to

the appropriate logic blocks. Each logic block receives 36

inputs from the PIM and their complements, allowing for 32-bit

operations to be implemented in a single pass through the

device. The wide number of inputs to the logic block also

improves the routing capacity of the Ultra37000 family.

Each logic block features a 72 x 87 programmable product

term array. This array accepts 36 inputs from the PIM, which

originate from macrocell feedbacks and device pins. Active

LOW and active HIGH versions of each of these inputs are

generated to create the full 72-input field. The 87 product

terms in the array can be created from any of the 72 inputs.

Of the 87 product terms, 80 are for general-purpose use for

the 16 macrocells in the logic block. Four of the remaining

seven product terms in the logic block are output enable (OE)

product terms. Each of the OE product terms controls up to

eight of the 16 macrocells and is selectable on an individual

macrocell basis. In other words, each I/O cell can select

between one of two OE product terms to control the output

buffer. The first two of these four OE product terms are

available to the upper half of the I/O macrocells in a logic block.

The other two OE product terms are available to the lower half

of the I/O macrocells in a logic block.

An important feature of the PIM is its simple timing. The propa-

gation delay through the PIM is accounted for in the timing

specifications for each device. There is no additional delay for

traveling through the PIM. In fact, all inputs travel through the

PIM. As a result, there are no route-dependent timing param-

eters on the Ultra37000 devices. The worst-case PIM delays

are incorporated in all appropriate Ultra37000 specifications.

Routing signals through the PIM is completely invisible to the

user. All routing is accomplished by software—no hand routing

is necessary. Warp^and third-party development packages

automatically route designs for the Ultra37000 family in a

matter of minutes. Finally, the rich routing resources of the

Ultra37000 family accommodate last minute logic changes

while maintaining fixed pin assignments.

The next two product terms in each logic block are dedicated

asynchronous set and asynchronous reset product terms. The

final product term is the product term clock. The set, reset, OE

and product term clock have polarity control to realize OR

functions in a single pass through the array.

Document #: 38-03007 Rev. *D

Page 3 of 64

1 234 5 6 7...64

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与5962-9952001QYA相关器件

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5962-9952101QYA	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952101QYX	CYPRESS	EE PLD, 12ns, CMOS, CQCC84, CERAMIC, LCC-84	获取价格
5962-9952102QYA	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952102QYX	CYPRESS	EE PLD, 10ns, CMOS, CQCC84, CERAMIC, LCC-84	获取价格
5962-9952201QYA	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952201QYX	CYPRESS	EE PLD, 15ns, CMOS, CQCC84, CERAMIC, LCC-84	获取价格

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