frontpage).Alsonotethatbothamplifiersareguaranteed
to be enabled if all three of these pins are unconnected.
Fig. 2 illustrates the differential mode of the CLC431's
disable feature for ECL-type logic. In order for this mode
V
to operate properly,
must be left floating while DIS
RTTL
Fig. 1 illustrates the single-ended mode of the CLC431's
disable feature for logic families such as TTL and CMOS.
VRTTL
and DIS are to be connected directly to the ECL gate as
illustrated. Applying a differential logic "high" (DIS - DIS
≥
0.4Volts) switches the tail current of the differential pair
In order to operate properly,
must be grounded,
thereby biasing DIS to approximately +1.4V through the
two internal series diodes. For single-ended operation,
DIS shouldbeleftfloating.ApplyingaTTLorCMOSlogic
"high" (i.e. >2.0Volts) to DIS will switch the tail current of
the differential pair to Q1 and "shut down" Q2 which
results in the disabling of that channel of the CLC431.
Alternatively,applyingalogic"low"(i.e.<0.8Volts)toDIS
will switch the tail current from Q1 to Q2 effectively
enabling that channel. If DIS is left floating under single-
endedoperation,thentheassociatedamplifierisguaran-
teed to be disabled.
from Q2 to Q1 and results in the disabling of that CLC431
channel. Alternatively, applying a differential logic "low"
≤
(DIS - DIS -0.4Volts) switches the tail current of the
differential pair from Q1 to Q2 and results in the enabling
of that same channel. The internal clamp, mentioned
above, also protects against excessive differential volt-
ages up to 30Volts while limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be cancelled and each contributes to the total DC offset
voltage at the output by the following equation:
Vnon-inv
+
-
Vout
Rf
Rf
Vinv
Voffset = ± Ibn Rs 1+
+ V 1+
+Ibi Rf
io
Rg
Rg
+VCC
+VCC
+VCC
TheinputresistorRs isthatresistanceseenwhenlooking
fromthenon-invertinginputbacktowardsthesource.For
inverting DC-offset calculations, the source resistance
seen by the input resistor Rg must be included in the
output offset calculation as a part of the non-inverting
gainequation.ApplicationnoteOA-7givesseveralcircuits
for DC offset correction.
100kΩ
100kΩ
DIS
DIS
TTL
CMOS
Q1
Q2
VRTTL
½CLC431
Layout Considerations
Itisrecommendedthatthedecouplingcapacitors (0.1µF
ceramicand6.8µFelectrolytic)shouldbeplacedasclose
as possible to the power supply pins to insure a proper
high-frequencylowimpedancebypass. Carefulattention
to circuit board layout is also necessary for best
performance. Of particular importance is the control of
parasitic capacitances (to ground) at the output and
invering input pins. See CLC431/432 Evaluation Board
literature for more information.
Fig. 1
The disable feature of the CLC431 is such that
DIS have common-mode input voltage ranges of (+VCC)
to (-VCC+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect
DIS
and
DIS
the
input from excessive input voltages that could
otherwise cause damage to the device. This condition
occurs when enough source current flows into the node
DIS
exceeds
so as to allow
to rise to VCC. This clamp is activated
by 1.5Volts and guarantees that
Applications Circuits
2:1 Video Mux (CLC431)
DIS
once
DIS
VDIS (ground referenced) does not exceed 4.7Volts.
Fig. 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75Ω system. Each
of the two CLC431's amplifiers is configured with a non-
inverting gain of +2V/V using 634Ω feedback (Rf) and
gain-setting(Rg)resistors.Thefeedbackresistorvalue is
lower than that recommended in order to compensate for
the reduction of loop-gain that results from the inclusion
of the 50Ω resistor (Ri) in the feedback loop. This 50Ω
resistor serves to isolate the output of the active channel
from the impedance of the inactive channel yet does not
affect the low output impedance of the active channel.
Vnon-inv
+
-
Vout
Vinv
+VCC
+VCC
+VCC
100kΩ
100kΩ
DIS
DIS
Q1
Q2
ECL
510Ω
-5V
VRTTL
V
1
Noticethatforproperoperation
(pin13)isgrounded
RTTL
½CLC431
VRTTL 2
and
(pin 9) is unconnected. The pins associated
with the disable feature are to be connected as follows:
DIS1 and DIS2 (pins 3 & 10) are connected together as
510Ω
-5V
well as DIS2 and
(pins 5 & 12). Channel 1 is
DIS1
selected with the application of a logic "low" to SELECT
while a logic "high" selects Channel 2.
Fig. 2
5
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