Datasheet > 5962-9451801MLA

5962-9451801MLA

更新时间： 2024-01-10 17:44:46

品牌	Logo	应用领域
亚德诺 - ADI		信息通信管理转换器
页数	文件大小	规格书
12页	184K
描述
LC2MOS Complete, Dual 12-Bit MDAC, (8 + 4) Loading Structure

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5962-9451801MLA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP, DIP24,.3	针数：	24
Reach Compliance Code：	not_compliant	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.06
Is Samacsys：	N	最大模拟输出电压：	10 V
最小模拟输出电压：	-10 V	转换器类型：	D/A CONVERTER
输入位码：	BINARY, OFFSET BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	R-GDIP-T24	JESD-609代码：	e0
最大线性误差 (EL)：	0.0244%	标称负供电电压：	-15 V
位数：	12	功能数量：	2
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP24,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	+-15 V
认证状态：	Qualified	筛选级别：	MIL-STD-883
座面最大高度：	5.715 mm	标称安定时间 (tstl)：	3 µs
子类别：	Other Converters	最大压摆率：	10 mA
标称供电电压：	15 V	表面贴装：	NO
技术：	BICMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT APPLICABLE	宽度：	7.62 mm
Base Number Matches：	1

5962-9451801MLA 数据手册

AD7837/AD7847

Channel-to-Channel Isolation

TERMINOLOGY

This is an ac error due to capacitive feedthrough from the V_REF

input on one DAC to V_OUTon the other DAC. It is measured

with the DAC latches loaded with all 0s.

Relative Accuracy (Linearity)

Relative accuracy, or endpoint linearity, is a measure of the

maximum deviation of the DAC transfer function from a

straight line passing through the endpoints. It is measured after

allowing for zero and full-scale errors and is expressed in LSBs

or as a percentage of full-scale reading.

Digital Feedthrough

Digital feedthrough is the glitch impulse injected from the digi-

tal inputs to the analog output when the data inputs change state,

but the data in the DAC latches is not changed.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB or less

over the operating temperature range ensures monotonicity.

For the AD7837, it is measured with LDAC held high. For the

AD7847, it is measured with CSA and CSB held high.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one converter due to a change in digital code on the DAC

latch of the other converter. It is specified in nV secs.

Zero Code Offset Error

Zero code offset error is the error in output voltage from V_OUTA

or V_OUTBwith all 0s loaded into the DAC latches. It is due to a

combination of the DAC leakage current and offset errors in the

output amplifier.

Digital-to-Analog Glitch Impulse

This is the voltage spike that appears at the output of the DAC

when the digital code changes, before the output settles to its

final value. The energy in the glitch is specified in nV secs and is

measured for a 1 LSB change around the major carry transition

(0111 1111 1111 to 1000 0000 0000 and vice versa).

Gain Error

Gain error is a measure of the output error between an ideal

DAC and the actual device output with all 1s loaded. It does

not include offset error.

Unity Gain Small Signal Bandwidth

Total Harmonic Distortion

This is the ratio of the root-mean-square (rms) sum of the har-

monics to the fundamental, expressed in dBs.

This is the frequency at which the small signal voltage output

from the output amplifier is 3 dB below its dc level. It is mea-

sured with the DAC latch loaded with all 1s.

Multiplying Feedthrough Error

Full Power Bandwidth

This is an ac error due to capacitive feedthrough from the V_REF

input to V_OUTof the same DAC when the DAC latch is loaded

with all 0s.

This is the maximum frequency for which a sinusoidal input

signal will produce full output at rated load with a distortion

less than 3%. It is measured with the DAC latch loaded with

all 1s.

AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)

Description

Mnemonic

Chip Select. Active low logic input. The device is selected when this input is active.

Amplifier Feedback Resistor for DAC A.

Reference Input Voltage for DAC A. This may be an ac or dc signal.

Analog Output Voltage from DAC A.

Analog Ground for DAC A.

Positive Power Supply.

R_FBA

V_REFA

V_OUTA

AGNDA

V_DD

V_SS

Negative Power Supply.

AGNDB

V_OUTB

V_REFB

DGND

R_FBB

Analog Ground for DAC B.

Analog Output Voltage from DAC B.

Reference Input Voltage for DAC B. This may be an ac or dc signal.

Digital Ground. Ground reference for digital circuitry.

Amplifier Feedback Resistor for DAC B.

Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to

write data to the input latches.

LDAC

DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when LDAC

is taken low.

17–20

21–24

DB7–DB4

DB3–DB0

Address Input. Most significant address input for input latches (see Table II).

Address Input. Least significant address input for input latches (see Table II).

Data Bit 7 to Data Bit 4.

Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8.

–4–

REV. C

1 2 345 6 7...12

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与5962-9451801MLA相关器件

型号	品牌	描述	获取价格	数据表
5962-9451801MLX	ETC	12-Bit Digital-to-Analog Converter	获取价格
5962-9451802MLA	ADI	LC2MOS Complete, Dual 12-Bit MDAC, Parallel Loading Structure	获取价格
5962-9451802MLX	ETC	12-Bit Digital-to-Analog Converter	获取价格
5962-94520	ETC	Monolithic Operational Amplifier In Isolated Flat Packs	获取价格
5962-9452001HXA	ETC	Operational Amplifier	获取价格
5962-9452001HXC	ETC	Operational Amplifier	获取价格

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