Datasheet > 5962-9317704VZX

5962-9317704VZX

更新时间： 2024-01-22 12:10:33

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
32页	194K
描述
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28,

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技术参数
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5962-9317704VZX 技术参数

生命周期：	Obsolete	零件包装代码：	DFP
包装说明：	DFP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.12
最长访问时间：	15 ns	周期时间：	25 ns
JESD-30 代码：	R-CDFP-F28	长度：	18.288 mm
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	3.3 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

5962-9317704VZX 数据手册

4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of

MIL-STD-883 and herein (see 1.5).

a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes

which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.

b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved

radiation hardness assurance plan and MIL-PRF-38535.

4.4.4.4 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be

required on class V devices (see 1.5 herein). SEP testing shall be performed on a technology process on the Standard

Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at inital qualification and after

any design or process changes which may affect the upset or latchup characteristics. The recommended test conditions

for SEP are as follows:

a.The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0°

< angle < 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.

b.The fluence shall be > 100 errors or > 10⁶ions/cm².

c. The flux shall be between 10²and 10⁵ions/cm²/s. The cross-section shall be verified to be flux independent by

measuring the cross-section at two flux rates which differ by at least an order of magnitude.

d.The particle range shall be > 20 microns in silicon.

e.The test temperature shall be +25°C and the maximum rated operating temperature +10°C.

f. Bias conditions shall be defined by the manufacturer for latchup measurements.

g.Test four devices with zero failures.

4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded

before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical

parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his

option, either perform delta measurements or within 24 hours after life test perform final electrical parameter tests,

subgroups 1, 7, 9.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device

classes Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.1 Replacability. Microcircuits covered by this drawing are intended for use for government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record

for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

SIZE

STANDARD

5962-93177

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

REVISION LEVEL

SHEET

DSCC FORM 2234

APR 97

1...26 27 282930 31 32

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与5962-9317704VZX相关器件

型号	品牌	描述	获取价格	数据表
5962-9317705QNC	MICROCHIP	FIFO, 16KX9, 30ns, Asynchronous, CMOS	获取价格
5962-9317705QTC	MICROCHIP	FIFO, 16KX9, 30ns, Asynchronous, CMOS, DIP-28	获取价格
5962-9317705QZX	WEDC	IC 16K X 9 OTHER FIFO, 30 ns, CDFP28, 0.400 INCH, FP-28, FIFO	获取价格
5962-9317705VNC	ATMEL	FIFO, 16KX9, 30ns, Asynchronous, CMOS, FP-28	获取价格
5962-9317705VUX	TEMIC	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格
5962-9317705VZA	TEMIC	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28	获取价格

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