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5962-9232406MYC PDF预览

5962-9232406MYC

更新时间： 2024-02-17 21:46:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 280K
描述
8KX8 NON-VOLATILE SRAM, 35ns, CQCC28, CERAMIC, LCC-28

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5962-9232406MYC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCN,Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：5.8最长访问时间：35 ns
其他特性：SOFTWARE STORE/RECALLJESD-30 代码：R-CQCC-N28
JESD-609代码：e4长度：13.97 mm
内存密度：65536 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8功能数量：1
端口数量：1端子数量：28
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：8KX8
输出特性：3-STATE可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：2.29 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：GOLD
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8.89 mmBase Number Matches：1

5962-9232406MYC 数据手册

 浏览型号5962-9232406MYC的Datasheet PDF文件第5页浏览型号5962-9232406MYC的Datasheet PDF文件第6页浏览型号5962-9232406MYC的Datasheet PDF文件第7页浏览型号5962-9232406MYC的Datasheet PDF文件第9页浏览型号5962-9232406MYC的Datasheet PDF文件第10页浏览型号5962-9232406MYC的Datasheet PDF文件第11页 
STK11C68  
Internally, RECALL is a two-step procedure. First,  
the SRAM data is cleared, and second, the nonvola-  
tile information is transferred into the SRAM cells.  
After the tRECALL cycle time the SRAM will once again  
be ready for READ and WRITE operations. The  
RECALL operation in no way alters the data in the  
Nonvolatile Elements. The nonvolatile data can be  
recalled an unlimited number of times.  
HARDWARE PROTECT  
The STK11C68 offers hardware protection against  
inadvertent STORE operation during low-voltage  
conditions. When VCC < VSWITCH, software STORE  
operations are inhibited.  
LOW AVERAGE ACTIVE POWER  
The STK11C68 draws significantly less current  
when it is cycled at times longer than 50ns. Figure 2  
shows the relationship between ICC and READ cycle  
time. Worst-case current consumption is shown for  
both CMOS and TTL input levels (commercial tem-  
perature range, VCC = 5.5V, 100% duty cycle on chip  
enable). Figure 3 shows the same relationship for  
WRITE cycles. If the chip enable duty cycle is less  
than 100%, only standby current is drawn when the  
chip is disabled. The overall average current drawn  
by the STK11C68 depends on the following items:  
1) CMOS vs. TTL input levels; 2) the duty cycle of  
chip enable; 3) the overall cycle rate for accesses;  
4) the ratio of READs to WRITEs; 5) the operating  
POWER-UP RECALL  
During power up, or after any low-power condition  
(VCC < VRESET), an internal RECALL request will be  
latched. When VCC once again exceeds the sense  
voltage of VSWITCH, a RECALL cycle will automatically  
be initiated and will take tRESTORE to complete.  
If the STK11C68 is in a WRITE state at the end of  
power-up RECALL, the SRAM data will be corrupted.  
To help avoid this situation, a 10K Ohm resistor  
should be connected either between W and system  
VCC or between E and system VCC.  
temperature; 6) the V level; and 7) I/O loading.  
cc  
100  
80  
100  
80  
60  
40  
20  
0
60  
TTL  
CMOS  
40  
TTL  
20  
CMOS  
0
50  
100  
150  
200  
50  
100  
150  
200  
Cycle Time (ns)  
Cycle Time (ns)  
Figure 2: I (max) Reads  
Figure 3: I (max) Writes  
CC  
CC  
March 2006  
8
Document Control # ML0007 rev 0.2  
1...56789101112

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