Datasheet > 放大器电路 > 采样保持电路> 5962-9201301MEA

5962-9201301MEA

更新时间： 2024-01-11 23:16:18

品牌	Logo	应用领域
亚德诺 - ADI		采样保持电路放大器放大器电路信息通信管理
页数	文件大小	规格书
8页	265K
描述
Four-Channel Sample-and-Hold Amplifier

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5962-9201301MEA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.33.00.01	风险等级：	5.78
Is Samacsys：	N	最长采集时间：	1 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最大下降率：	1 V/s
JESD-30 代码：	R-GDIP-T16	负供电电压上限：	-15 V
标称负供电电压 (Vsup)：	-12 V	功能数量：	4
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Qualified
采样并保持/跟踪并保持：	SAMPLE	筛选级别：	MIL-PRF-38535
子类别：	Sample and Hold Circuit	供电电压上限：	15 V
标称供电电压 (Vsup)：	12 V	表面贴装：	NO
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子位置：	DUAL	Base Number Matches：	1

5962-9201301MEA 数据手册

AD684

The AD684 does not provide separate analog and digital ground

leads as is the case with most A-to-D converters. The common

pin is the single ground terminal for the device. It is the refer-

ence point for the sampled input voltage and the held output

voltage and also the digital ground return path. The common

pin should be connected to the reference (analog) ground of the

A-to-D converter with a separate ground lead. Since the analog

and digital grounds in the 684 are connected internally, the

common pin should also be connected to the digital ground,

which is usually tied to analog common at the A-to-D converter.

Figure 4 illustrates the recommended decoupling and grounding

practice.

A graph showing the magnitude of the jitter induced error vs.

frequency of the input signal is given in Figure 6.

The accuracy in sampling high frequency signals is also con-

strained by the distortion and noise created by the sample-and-

hold. The level of distortion increases with frequency and

reduces the “effective number of bits” of the conversion.

Measurements of Figures 7 and 8 were made using a 14-bit

A-to-D converter with V_IN= 10 V p-p and a sample frequency

of 100 kSPS.

NOISE CHARACTERISTICS

Designers of data conversion circuits must also consider the

effect of noise sources on the accuracy for the data acquisition

system. A sample-and-hold amplifier that precedes the A-to-D

converter introduces some noise and represents another source

of uncertainty in the conversion process. The noise from the

AD684 is specified as the total output noise, which includes

both the sampled wideband noise of the SHA in addition to the

band limited output noise. The total output noise is the rms

sum of the sampled dc uncertainty and the hold mode noise. A

plot of the total output noise vs. the equivalent input bandwidth

of the converter being used is given in Figure 5.

Figure 6. Error Magnitude vs. Frequency

Figure 7. Total Harmonic Distortion vs. Frequency

Figure 8. Signal/(Noise and Distortion) vs. Frequency

Figure 5. RMS Noise vs. Input Bandwidth of ADC

DRIVING THE ANALOG INPUTS

For best performance, it is important to drive the AD684 analog

inputs from a low impedance signal source. This enhances the

sampling accuracy by minimizing the analog and digital

crosstalk. Signals which come from higher impedance sources

(e.g., over 5k ohms) will have a relatively higher level of

crosstalk. For applications where signals have high source

impedance, an operational amplifier buffer in front of the

AD684 is required. The AD713 (precision quad BiFET op

amp) is recommended for these applications.

HIGH FREQUENCY SAMPLING

Aperture jitter and distortion are the primary factors which limit

frequency domain performance of a sample-and-hold amplifier.

Aperture jitter modulates the phase of the hold command and

produces an effective noise on the sampled analog input. The

magnitude of the jitter induced noise is directly related to the

frequency of the input signal.

REV. A

–7–

1...4 5 678

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