AD684
DEFINITIONS OF SPECIFICATIONS
Tracking Mode Offset — The difference between the input
and output signals when the SHA is in the track mode.
Acquisition Time — The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Nonlinearity — The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Small Signal Bandwidth — The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Gain Error — Deviation from a gain of +1 on the transfer
function of input vs. held output.
Full Power Bandwidth — The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Interchannel Isolation — The level of crosstalk between
adjacent channels while in the sample (track) mode with a full
scale 100 kHz input signal.
Effective Aperture Delay — The difference between the
switch delay and the analog delay of the SHA channel. A
negative number indicates that the analog portion of the overall
delay is greater than the switch portion. This effective delay
represents the point in time, relative to the hold command, that
the input signal will be sampled.
Interchannel Aperture Offset — The variation in aperture
time between the four channels for a simultaneous hold
command.
Differential Offset — The difference in hold mode offset
between the four SHA channels.
Power Supply Rejection Ratio — A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Aperture Jitter — The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Sampled dc Uncertainty — The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Settling Time —The time required for the output to
settle to within a specified level of accuracy of its final held
value after the hold command has been given.
Hold Mode Noise — The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Droop Rate — The drift in output voltage while in the hold
mode.
Total Output Noise — The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Feedthrough — The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Output Drive Current — The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Hold Mode Offset — The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
FUNCTIONAL DESCRIPTION
The AD684 is a complete quad sample-and-hold amplifier that
provides high speed sampling to 12-bit accuracy in less than 1µs.
The AD684 is completely self-contained, including on-chip
hold capacitors, and requires no external components or
adjustments to perform the sampling function. Each SHA
channel can operate independently, having its own input, output
and sample/hold command. Both inputs and outputs are treated
as single ended signals, referred to common.
The AD684 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. To the right is a block diagram
of the AD684.
Functional Block Diagram
REV. A
–5–
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