HD-15531
o
o
AC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HD-15530-9)
CC
A
A
o
o
T
= -55 C to +125 C (HD-15530-8)
HD-15531B
HD-15531
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
TEST CONDITIONS (NOTE 2)
ENCODER TIMING
FEC
FESC
FED
TMR
TE1
Encoder Clock Frequency
Send Clock Frequency
Encoder Data Rate
Master Reset Pulse Width
Shift Clock Delay
Serial Data Setup
Serial Data Hold
Enable Setup
-
-
15
-
-
30
MHz
MHz
MHz
ns
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
L
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
2.5
5.0
= 4.5V and 5.5V, C = 50pF
L
-
1.25
-
2.5
= 4.5V and 5.5V, C = 50pF
L
150
-
-
150
-
-
= 4.5V and 5.5V, C = 50pF
L
125
80
ns
= 4.5V and 5.5V, C = 50pF
L
TE2
75
75
90
100
55
150
0
-
50
50
90
100
55
150
0
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE3
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE4
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE5
Enable Pulse Width
Sync Setup
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE6
-
-
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE7
Sync Pulse Width
Send Data Delay
Bipolar Output Delay
Enable Hold
ns
= 4.5V and 5.5V, C = 50pF
L
TE8
50
130
-
50
130
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE9
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
TE10
TE11
10
95
10
95
ns
= 4.5V and 5.5V, C = 50pF
L
Sync Hold
-
-
ns
= 4.5V and 5.5V, C = 50pF
L
DECODER TIMING
FDC
FDS
Decoder Clock Frequency
-
-
15
-
-
30
MHz
MHz
MHz
ns
V
V
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
L
CC
CC
CC
CC
CC
CC
CC
CC
Decoder Sync Clock
2.5
5.0
= 4.5V and 5.5V, C = 50pF
L
FDD
Decoder Data Rate
-
1.25
-
2.5
= 4.5V and 5.5V, C = 50pF
L
TDR
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse
150
75
10
150
-
-
-
-
-
150
75
10
150
-
-
-
-
-
= 4.5V and 5.5V, C = 50pF
L
TDRS
TDRH
TMR
TD1
ns
= 4.5V and 5.5V, C = 50pF
L
ns
= 4.5V and 5.5V, C = 50pF
L
ns
= 4.5V and 5.5V, C = 50pF
L
Bipolar Data Pulse Width
TDC + 10
(Note 1)
TDC + 10
(Note 1)
ns
= 4.5V and 5.5V, C = 50pF
L
TD3
One Zero Overlap
-
TDC - 10
(Note 1)
-
TDC - 10
(Note 1)
ns
V
= 4.5V and 5.5V, C = 50pF
CC L
TD6
TD7
Sync Delay (ON)
-20
0
110
110
80
-20
0
110
110
80
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
V
V
= 4.5V and 5.5V, C = 50pF
L
CC
CC
CC
CC
CC
CC
CC
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OFF)
= 4.5V and 5.5V, C = 50pF
L
TD8
-
-
= 4.5V and 5.5V, C = 50pF
L
TD9
0
110
110
110
75
0
110
110
110
75
= 4.5V and 5.5V, C = 50pF
L
TD10
TD11
TD12
Take Data Delay (OFF)
Valid Word Delay
0
0
= 4.5V and 5.5V, C = 50pF
L
0
0
= 4.5V and 5.5V, C = 50pF
L
Sync Clock to Shift Clock
Delay
-
-
= 4.5V and 5.5V, C = 50pF
L
TD13
Sync Data Setup
75
-
75
-
ns
V
= 4.5V and 5.5V, C = 50pF
CC L
NOTES:
1. TDC = Decoder clock period = 1/FDC.
2. AC Testing as follows: Input levels: V = 70% V , V = 20% V ; Input rise/fall times driven at 1ns/V; Timing Reference
IH CC IL CC
levels: V /2; Output load: C = 50pF.
CC
L
12