Datasheet > 5962-8999001EA

5962-8999001EA

更新时间： 2024-02-03 10:27:27

品牌	Logo	应用领域
德州仪器 - TI		逻辑集成电路
页数	文件大小	规格书
14页	243K
描述
High-Speed CMOS Logic Digital Phase-Locked Loop

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技术参数
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5962-8999001EA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.27	系列：	HC/UH
JESD-30 代码：	R-GDIP-T16	逻辑集成电路类型：	LOGIC CIRCUIT
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Qualified
筛选级别：	MIL-STD-883	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	4.5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED

5962-8999001EA 数据手册

CD54HC297, CD74HC297,

CD74HCT297

Data sheet acquired from Harris Semiconductor

SCHS177B

High-Speed CMOS Logic

Digital Phase-Locked Loop

November 1997 - Revised May 2003

Features

Description

• Digital Design Avoids Analog Compensation Errors

• Easily Cascadable for Higher Order Loops

The ’HC297 and CD74HCT297 are high-speed silicon gate

CMOS devices that are pin-compatible with low power Schot-

tky TTL (LSTTL).

[ /Title

(CD74

HC297

CD74

HCT29

• Useful Frequency Range

These devices are designed to provide a simple, cost-effec-

tive solution to high-accuracy, digital, phase-locked-loop appli-

cations. They contain all the necessary circuits, with the

exception of the divide-by-N counter, to build first-order

phase-locked-loops.

- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)

- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)

• Dynamically Variable Bandwidth

• Very Narrow Bandwidth Attainable

• Power-On Reset

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase

detectors (ECPD) are provided for maximum flexibility. The

input signals for the EXCLUSIVE-OR phase detector must

have a 50% duty factor to obtain the maximum lock-range.

/Sub-

ject

• Output Capability

- Standard. . . . . . . . . . . . . . . . . . . . XORPD

, ECPD

OUT

(High-

Speed

CMOS

Logic

Digi-

tal

Proper partitioning of the loop function, with many of the build-

ing blocks external to the package, makes it easy for the

designer to incorporate ripple cancellation (see Figure 2) or to

cascade to higher order phase-locked-loops.

- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The length of the up/down K-counter is digitally programmable

according to the K-counter function table. With A, B, C and D

all LOW, the K-counter is disabled. With A HIGH and B, C and

D LOW, the K-counter is only three stages long, which widens

the bandwidth or capture range and shortens the lock time of

the loop. When A, B, C and D are all programmed HIGH, the

K-counter becomes seventeen stages long, which narrows

the bandwidth or capture range and lengthens the lock time.

Real-time control of loop bandwidth by manipulating the A to

D inputs can maximize the overall performance of the digital

phase-locked-loop.

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

Phase-

Locked

• ’HC297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V

- High Noise ImmunityN = 30%, N = 30% of V at 5V

IL IH CC

• CD74HCT297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V

- Direct LSTTL Input Logic Compatibility

The ’HC297 and CD74HCT297 can perform the classic first

order phase-locked-loop function without using analog com-

ponents. The accuracy of the digital phase-locked-loop

= 0.8V (Max), V = 2V (Min)

- CMOS Input Compatibility I ≤ 1µA at V , V

OL OH

(DPLL) is not affected by V

and temperature variations but

Pinout

depends solely on accuracies of the K-clock and loop propa-

gation delays.

CD54HC297

(CERDIP)

CD74HC297, CD74HCT29

(PDIP)

Ordering Information

TOP VIEW

PART NUMBER

CD54HC297F3A

CD74HC297E

TEMP. RANGE ( C)

-55 to 125

PACKAGE

16 Ld CERDIP

16 Ld PDIP

16 V

15 C

14 D

-55 to 125

CTR

CD74HCT297E

-55 to 125

16 Ld PDIP

13 φA

I/D

12 ECPD

OUT

D/U

11 XORPD

OUT

10 φB

I/D

OUT

φA

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...14

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