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5962-89841063X#N/A PDF预览

5962-89841063X#N/A

更新时间: 2024-02-13 00:14:49
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程逻辑
页数 文件大小 规格书
16页 622K
描述
Flash PLD

5962-89841063X#N/A 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknown可编程逻辑类型:FLASH PLD
Base Number Matches:1

5962-89841063X#N/A 数据手册

 浏览型号5962-89841063X#N/A的Datasheet PDF文件第2页浏览型号5962-89841063X#N/A的Datasheet PDF文件第3页浏览型号5962-89841063X#N/A的Datasheet PDF文件第4页浏览型号5962-89841063X#N/A的Datasheet PDF文件第6页浏览型号5962-89841063X#N/A的Datasheet PDF文件第7页浏览型号5962-89841063X#N/A的Datasheet PDF文件第8页 
Atmel ATF22V10B  
6.  
7.  
Input Test Waveforms and Measurement Levels  
tR, tF < 3ns  
Output Test Loads  
Commercial  
Military  
* All except -7 which is R2 = 300  
8.  
9.  
Pin Capacitance  
f = 1MHz, T = 25°C(1)  
Typ  
5
Max  
Units  
pF  
Conditions  
CIN  
8
VIN = 0V  
COUT  
6
8
pF  
VOUT = 0V  
Note:  
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested  
Power-up Reset  
The registers in the Atmel® ATF22V10B are designed to reset during power-up. At a point delayed slightly from  
VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the out-  
put buffer.  
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the following conditions are required:  
1. The VCC rise must be monotonic  
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high  
3. The clock must remain stable during tPR  
5
0250M–PLD–7/10  

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