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PALCE22V10
Commercial Switching Characteristics PALCE22V10 (continued)[2, 7]
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tS1
tS2
Input or Feedback Set-Up Time
3
4
5
6
6
7
10
10
15
15
ns
ns
Synchronous Preset Set-Up
Time
tH
Input Hold Time
0
0
10
3
0
12
3
0
20
6
0
30
ns
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
7
tWH
tWL
fMAX1
2.5
2.5
143
13
ns
3
3
6
13
ns
External Maximum
100
76.9
55.5
33.3
MHz
Frequency (1/(tCO + tS))[11]
fMAX2
fMAX3
tCF
Data Path Maximum Frequency 200
(1/(tWH + tWL))[6, 12]
166
133
142
111
83.3
68.9
35.7
38.5
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,13]
181
Register Clock to
2.5
7.5
2.5
12
3
4.5
20
13
25
Feedback Input[6,14]
tAW
tAR
Asynchronous Reset Width
8
4
8
5
10
6
15
10
25
25
ns
ns
Asynchronous Reset
Recovery Time
tAP
Asynchronous Reset to
Registered Output Delay
13
ns
ns
µs
tSPR
tPR
Synchronous Preset
Recovery Time
Power-up Reset Time[6,15]
4
1
6
1
8
1
10
1
15
1
[2, 7]
Military and Industrial Switching Characteristics PALCE22V10
22V10-10
22V10-15
Min. Max.
22V10-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
3
10
3
15
3
25
ns
Propagation Delay[8]
tEA
tER
tCO
tS1
tS2
tH
Input to Output Enable Delay[9]
Input to Output Disable Delay[10]
Clock to Output Delay[8]
Input or Feedback Set-up Time
Synchronous Preset Set-up Time
Input Hold Time
10
10
7
15
15
8
25
25
15
ns
ns
2
6
2
10
10
0
2
18
18
0
ns
ns
7
ns
0
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
12
3
20
6
33
14
14
30.3
ns
tWH
tWL
ns
3
6
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))[11]
76.9
50.0
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12 ]
142
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f internal (1/f ) as measured (see Note above) minus t .
MAX
MAX3
S
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in V must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
CC
Document #: 38-03027 Rev. *B
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