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5962-89841033X PDF预览

5962-89841033X

更新时间: 2024-02-11 21:55:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
15页 537K
描述
Highperformance EE PLD

5962-89841033X 技术参数

生命周期:Active包装说明:LCC-28
Reach Compliance Code:compliant风险等级:5.83
可编程逻辑类型:FLASH PLD

5962-89841033X 数据手册

 浏览型号5962-89841033X的Datasheet PDF文件第2页浏览型号5962-89841033X的Datasheet PDF文件第3页浏览型号5962-89841033X的Datasheet PDF文件第4页浏览型号5962-89841033X的Datasheet PDF文件第6页浏览型号5962-89841033X的Datasheet PDF文件第7页浏览型号5962-89841033X的Datasheet PDF文件第8页 
ATF22V10B  
Input Test Waveforms and  
Measurement Levels  
Output Test Loads  
Commercial  
Military  
tR, tF < 3 ns  
* All except -7 which is R2 = 300Ω  
Pin Capacitance  
f = 1 MHz, T = 25°C(1)  
Typ  
5
Max  
8
Units  
pF  
Conditions  
CIN  
VIN = 0V  
COUT  
6
8
pF  
VOUT = 0V  
Note:  
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.  
Power-up Reset  
The registers in the ATF22V10Bs are designed to reset  
during power-up. At a point delayed slightly from VCC cross-  
ing VRST, all registers will be reset to the low state. The  
output state will depend on the polarity of the output buffer.  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the  
following conditions are required:  
1. The VCC rise must be monotonic,  
2. After reset occurs, all input and feedback setup times  
must be met before driving the clock pin high, and  
Parameter  
Description  
Typ  
Max  
Units  
3. The clock must remain stable during tPR  
.
Power-up  
Reset Time  
tPR  
600  
1,000  
ns  
Preload of Registered Outputs  
Power-up  
Reset  
Voltage  
The ATF22V10B’s registers are provided with circuitry to  
allow loading of each register with either a high or a low.  
This feature will simplify testing since any state can be  
forced into the registers to control test sequencing. A  
JEDEC file with preload is generated when a source file  
with vectors is compiled. Once downloaded, the JEDEC file  
preload sequence will be done automatically by most of the  
approved programmers after the programming.  
VRST  
3.8  
4.5  
V
Security Fuse Usage  
A single fuse is provided to prevent unauthorized copying  
of the ATF22V10B fuse patterns. Once programmed, fuse  
verify and preload are inhibited. However, the 64-bit User  
Signature remains accessible.  
The security fuse should be programmed last, as its effect  
is immediate.  
5

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