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5962-8865801XA PDF预览

5962-8865801XA

更新时间： 2024-02-10 22:56:17
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
12页 165K
描述
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP32, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-32, Analog to Digital Converter

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5962-8865801XA 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：32
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.56
Is Samacsys：N最大模拟输入电压：10 V
最小模拟输入电压：-10 V最长转换时间：6 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：R-XDIP-T32
JESD-609代码：e0长度：40.945 mm
最大线性误差 (EL)：0.0183%标称负供电电压：-15 V
模拟输入通道数量：1位数：12
功能数量：1端子数量：32
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：BINARY, OFFSET BINARY输出格式：PARALLEL, WORD
封装主体材料：UNSPECIFIED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified采样并保持/跟踪并保持：SAMPLE
筛选级别：MIL-PRF-38534座面最大高度：7.11 mm
标称供电电压：15 V表面贴装：NO
温度等级：MILITARY端子面层：TIN LEAD
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：15.24 mm
Base Number Matches：1

5962-8865801XA 数据手册

 浏览型号5962-8865801XA的Datasheet PDF文件第3页浏览型号5962-8865801XA的Datasheet PDF文件第4页浏览型号5962-8865801XA的Datasheet PDF文件第5页浏览型号5962-8865801XA的Datasheet PDF文件第7页浏览型号5962-8865801XA的Datasheet PDF文件第8页浏览型号5962-8865801XA的Datasheet PDF文件第9页 
AD578/AD579  
ORDERING GUIDE1  
Conversion  
Speed  
Temperature  
Range  
Package  
Option2  
Model  
Resolution  
AD578JN (JD)  
AD578KN (KD)  
AD578LN (LD)  
AD578SD  
12 Bits  
12 Bits  
12 Bits  
12 Bits  
12 Bits  
12 Bits  
12 Bits  
10 Bits  
10 Bits  
10 Bits  
10 Bits  
6.0 ms  
4.5 ms  
3.0 ms  
6.0 ms  
4.5 ms  
6.0 ms  
4.5 ms  
2.2 ms  
1.8 ms  
1.8 ms  
1.8 ms  
0∞C to +70∞C  
0∞C to +70∞C  
0∞C to +70∞C  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
DH-32B  
–55∞C to +125∞C  
–55∞C to +125∞C  
–55∞C to +125∞C  
–55∞C to +125∞C  
0∞C to +70∞C  
0∞C to +70∞C  
–55∞C to +125∞C  
–55∞C to +125∞C  
AD578TD  
AD578SD/883B  
AD578TD/883B  
AD579JN  
AD579KN  
AD579TD  
AD579TD/883B  
NOTES  
1For ±12 V operation “Z” Version, order AD578ZTD.  
2DH = Side Brazed Ceramic DIP.  
200ns, min  
THEORY OF OPERATION  
CONVERT  
START  
The AD578 is a complete pretrimmed 12-bit A/D converter  
that requires no external components to provide the successive  
approximation analog-to-digital conversion function. A block  
diagram of the AD578/AD579 is shown in Figure 1.  
200ns  
80ns  
CLOCK  
160ns  
10ns  
100ns  
EOC  
AD578/AD579  
(AD578)  
BIT 1  
1
2
3
4
5
6
7
8
9
32  
–15V  
BIT 12  
(AD578)  
BIT 11  
31 +15V  
BIT 2  
BIT 3  
100⍀  
20k⍀  
30 ANALOG GND  
BIT 10  
BIT 9  
BIT 8  
BIT 7  
BIT 6  
BIT 5  
20k⍀  
5k⍀  
29  
28  
ZERO ADJ  
5k⍀  
20V SPAN INPUT  
BIT 4  
BIT 5  
BIT 6  
BIT 7  
BIT 8  
BIT 9  
27 10V SPAN INPUT  
10k⍀  
26  
25  
BIPOLAR OFFSET  
GAIN (REF IN)  
24 REF OUT  
BIT 4  
BIT 3 10  
BIT 2 11  
BIT 1 12  
BIT 1 13  
23 SERIAL OUT  
22  
SERIAL OUT  
21 CONVERT START  
20 EOC  
SHORT  
14  
15  
19 CLOCK IN  
18 CLOCK OUT  
17 CLOCK ADJ  
CYCLE  
DIGITAL  
GND  
SAR  
CLOCK  
BIT 10  
BIT 11  
+5V 16  
COMPARATOR  
Figure 1. AD578/AD579 Functional Block Diagram and  
Pinout  
BIT 12  
SERIAL  
OUT  
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12  
When the control section is commanded to initiate a conversion,  
it enables the clock and resets the successive approximation regis-  
ter (SAR). The SAR, timed by the clock, sequences through the  
conversion cycle and returns an end-of-convert flag to the control  
section. The control section disables the clock and brings the  
output status flag low. The data bits are valid on the falling  
edge of the clock pulse starting with t1 and ending with t12  
(Figures 2a and 2b), and accurately represent the input signal  
to within ±1/2 LSB.  
CLOCK  
INTERNAL: CONNECT CLOCK OUT (18) TO CLOCK IN (19)  
EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19)  
CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH  
MINIMUM PERIOD,T OF 100ns.  
MIN  
NOTE  
THE RISING EDGE OF CONVERT START PULSE RESETS THE MSB TO ZERO,  
AND THE LSBs TO ONE.THE TRAILING EDGE INITIATES CONVERSION.  
Figure 2a. AD578 Timing Diagram  
REV. B  
–6–  
1...3456789...12

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