STK14C88C
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power-up. This pull-up is
only effective if the WE signal is tristate during power-up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
Device Operation
The STK14C88C nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The STK14C88C
supports infinite reads and writes similar to a typical SRAM. In
addition, it provides infinite RECALL operations from the
nonvolatile cells and up to 1 million STORE operations. Refer to
the Truth Table For SRAM Operations on page 16 for a complete
description of read and write modes.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 2. AutoStore Mode
VCC
The STK14C88C performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0–14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
0.1 uF
is initiated by CE or OE, the outputs are valid at tACE or at tDOE
,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
VCC
WE
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
VCAP
VSS
Hardware STORE Operation
The STK14C88C provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the STK14C88C conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a write to the
SRAM has taken place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
AutoStore Operation
The STK14C88C stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power-down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the STK14C88C.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the STK14C88C. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 5. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Document Number: 002-23965 Rev. *A
Page 4 of 21
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