Datasheet > 5962-1821101QXC

5962-1821101QXC

更新时间： 2023-12-06 20:08:48

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
21页	447K
描述
nvSRAM (non-volatile SRAM)

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5962-1821101QXC 数据手册

STK14C88C

Pinout

Figure 1. 32-pin CDIP pinout

V_CAP

V_CC

A₁₄

HSB

A₁₂

A₇

A₁₃

A₈

A₉

A₆

A₅

A₄

A₃

A₁₁

(TOP)

A₂

A₁₀

A₁

A₀

DQ₇

DQ₀

DQ₁

DQ₂

V_SS

DQ₆

DQ₅

DQ₄

DQ₃

Pin Definitions

Alternate

Pin Name

I/O Type

Description

A₀–A₁₄

DQ₀–DQ₇

Input

Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.

Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.

Input

Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O

pins is written to the specific address location.

Input

Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers

during read cycles. I/O pins are tri-stated on deasserting OE HIGH.

V_SS

V_CC

Ground

Ground for the device. Must be connected to the ground of the system.

Power supply Power supply inputs to the device.

Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE

is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE

operation. After each Hardware and Software STORE operation HSB is driven HIGH for a

short time (t_HHHD) with standard output high current and then a weak internal pull-up resistor

keeps this pin HIGH (external pull-up resistor connection is optional).

HSB

V_CAP

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from

SRAM to nonvolatile elements.

No connect No connect. This pin is not connected to the die.

Document Number: 002-23965 Rev. *A

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