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5962-0620703Q2A PDF预览

5962-0620703Q2A

更新时间: 2024-02-10 21:19:52
品牌 Logo 应用领域
英特矽尔 - INTERSIL 驱动器接口集成电路
页数 文件大小 规格书
9页 195K
描述
【15kV ESD Protected, +3.3V, 1Microamp, 250kbps, RS-232 Transmitters/Receivers

5962-0620703Q2A 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.6
Is Samacsys:N差分输出:NO
驱动器位数:3输入特性:SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER接口标准:EIA-232; TIA-232; V.24; V.28
JESD-30 代码:S-CQCC-N20长度:8.89 mm
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
接收器位数:5筛选级别:MIL-PRF-38535 Class Q
座面最大高度:2.54 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

5962-0620703Q2A 数据手册

 浏览型号5962-0620703Q2A的Datasheet PDF文件第3页浏览型号5962-0620703Q2A的Datasheet PDF文件第4页浏览型号5962-0620703Q2A的Datasheet PDF文件第5页浏览型号5962-0620703Q2A的Datasheet PDF文件第6页浏览型号5962-0620703Q2A的Datasheet PDF文件第7页浏览型号5962-0620703Q2A的Datasheet PDF文件第8页 
5962-0620701Q3A, 5962-0620702Q3A, 5962-0620703Q2A, 5962-0620704Q2A  
Ceramic Leadless Chip Carrier Packages (CLCC)  
J20.A MIL-STD-1835 CQCC1-N20 (C-2)  
0.010 S E H S  
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE  
D
INCHES  
MIN  
MILLIMETERS  
D3  
SYMBOL  
A
MAX  
0.100  
0.088  
-
MIN  
1.52  
1.27  
-
MAX  
2.54  
2.23  
-
NOTES  
o
j x 45  
0.060  
0.050  
-
6, 7  
A1  
B
-
-
B1  
B2  
B3  
D
0.022  
0.028  
0.56  
0.71  
2, 4  
-
0.072 REF  
1.83 REF  
E3  
E
B
0.006  
0.342  
0.022  
0.358  
0.15  
8.69  
0.56  
9.09  
-
-
D1  
D2  
D3  
E
0.200 BSC  
0.100 BSC  
5.08 BSC  
2.54 BSC  
-
-
o
h x 45  
-
0.358  
0.358  
-
9.09  
9.09  
2
-
0.010 S E F S  
A1  
0.342  
8.69  
E1  
E2  
E3  
e
0.200 BSC  
0.100 BSC  
0.358  
0.050 BSC  
0.015  
5.08 BSC  
2.54 BSC  
9.09  
1.27 BSC  
0.38  
1.02 REF  
0.51 REF  
-
A
-
PLANE 2  
PLANE 1  
-
-
2
-
-E-  
e1  
h
-
-
2
5
5
-
0.040 REF  
0.020 REF  
j
0.007 M E F S H S  
L
0.045  
0.055  
0.055  
0.095  
0.015  
1.14  
1.14  
1.91  
0.08  
1.40  
1.40  
2.41  
0.38  
L1  
L2  
L3  
ND  
NE  
N
0.045  
0.075  
0.003  
-
B1  
e
-
L3  
L
-H-  
-
5
5
5
5
3
3
3
20  
20  
Rev. 0 5/18/94  
-F-  
NOTES:  
B3  
E1  
1. Metallized castellations shall be connected to plane 1 terminals  
and extend toward plane 2 across at least two layers of ceramic  
or completely across all of the ceramic layers to make electrical  
connection with the optional plane 2 terminals.  
L2  
E2  
B2  
2. Unless otherwise specified, a minimum clearance of 0.015 inch  
(0.38mm) shall be maintained between all metallized features  
(e.g., lid, castellations, terminals, thermal pads, etc.)  
L1  
3. Symbol “N” is the maximum number of terminals. Symbols “ND”  
and “NE” are the number of terminals along the sides of length  
“D” and “E”, respectively.  
D2  
e1  
D1  
4. The required plane 1 terminals and optional plane 2 terminals (if  
used) shall be electrically connected.  
5. The corner shape (square, notch, radius, etc.) may vary at the  
manufacturer’s option, from that shown on the drawing.  
6. Chip carriers shall be constructed of a minimum of two ceramic  
layers.  
7. Dimension “A” controls the overall package thickness. The maxi-  
mum “A” dimension is package height before being solder dipped.  
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
9. Controlling dimension: INCH.  
FN6297.0  
May 31, 2006  
9

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