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5962-02A0201QXX PDF预览

5962-02A0201QXX

更新时间： 2024-01-11 21:45:22
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
页数 文件大小 规格书
67页 1014K
描述
Serial I/O Controller, 3 Channel(s), 25MBps, CMOS, PQFP100, CERAMIC, MQFP-100

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5962-02A0201QXX 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFF,针数：100
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.72地址总线宽度：
边界扫描：YES最大时钟频率：5 MHz
最大数据传输速率：25 MBps外部数据总线宽度：16
JESD-30 代码：S-PQFP-F100长度：19.05 mm
低功率模式：NO串行 I/O 数：3
端子数量：100最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFF封装形状：SQUARE
封装形式：FLATPACK认证状态：Not Qualified
座面最大高度：2.67 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
宽度：19.05 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

5962-02A0201QXX 数据手册

 浏览型号5962-02A0201QXX的Datasheet PDF文件第4页浏览型号5962-02A0201QXX的Datasheet PDF文件第5页浏览型号5962-02A0201QXX的Datasheet PDF文件第6页浏览型号5962-02A0201QXX的Datasheet PDF文件第8页浏览型号5962-02A0201QXX的Datasheet PDF文件第9页浏览型号5962-02A0201QXX的Datasheet PDF文件第10页 
TS80C51U2  
TS83C51U2  
TS87C51U2  
Table 3. Pin Description for 40/44 pin packages  
PIN NUMBER  
MNEMONIC  
NAME AND FUNCTION  
TYPE  
DIL LCC VQFP 1.4  
Reset  
9
10  
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running,  
resets the device. An internal diffused resistor to V permits a power-on reset  
SS  
using only an external capacitor to V  
If the hardware watchdog reaches its  
CC.  
time-out, the reset pin becomes an output during the time the internal reset is  
activated.  
ALE/PROG  
30  
33  
27  
O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte  
of the address during an access to external memory. In normal operation, ALE  
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,  
and can be used for external timing or clocking. Note that one ALE pulse is  
skipped during each access to external data memory. This pin is also the program  
pulse input (PROG) during EPROM programming. ALE can be disabled by  
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal  
fetches.  
PSEN  
29  
31  
32  
35  
26  
29  
O
Program Store ENable: The read strobe to external program memory. When  
executing code from the external program memory, PSEN is activated twice each  
machine cycle, except that two PSEN activations are skipped during each access  
to external data memory. PSEN is not activated during fetches from internal  
program memory.  
EA/V  
I
External Access Enable/Programming Supply Voltage: EA must be externally  
held low to enable the device to fetch code from external program memory  
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is  
held high, the device executes from internal program memory unless the program  
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must  
be held low for ROMless devices. This pin also receives the 12.75V programming  
PP  
supply voltage (V ) during EPROM programming. If security level 1 is  
PP  
programmed, EA will be internally latched on Reset.  
XTAL1  
19  
21  
15  
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal  
clock generator circuits.  
XTAL2  
RxD_1  
18  
-
20  
12  
14  
6
O
I
Crystal 2: Output from the inverting oscillator amplifier  
Serial Input for UART_1. For 44-pin package only.  
Serial Ouput for UART_1. This pin is pulled up by a 100K resistor when not  
selected. For 44-pin package only.  
TxD_1  
-
34  
28  
O
Rev. D - 15 January, 2001  
7
1...45678910...67

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