82C54
The status register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back command.)
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
INTERNAL BUS
Operational Description
CONTROL
WORD
STATUS
LATCH
General
REGISTER
CR
CR
L
M
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
STATUS
REGISTER
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused counters need not be programmed.
CE
CONTROL
LOGIC
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
OL
OL
L
M
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
GATE n
CLK n OUT n
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally
“follow” the CE, but if a suitable Counter Latch Command is
sent to the 82C54, the latches “latch” the present count until
read by the CPU and then return to “following” the CE. One
latch at a time is enabled by the counter’s Control Logic to drive
the internal bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself cannot be
read; whenever you read the count, it is the OL that is being
read.
ADDRESS BUS (16)
A1 A0
CONTROL BUS
I/OR I/OW
DATA BUS (8)
8
RD
WR
CS
D0 - D7
82C54
A0
A1
COUNTER
0
COUNTER
1
COUNTER
2
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE
simultaneously. CRM and CRL are cleared when the Counter is
programmed for one byte counts (either most significant byte
only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is
written, it is written into the CR.
OUTGATE CLK OUTGATE CLK OUTGATE CLK
FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant
byte only, or least significant byte and then most significant
byte).
7
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
