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56F84462VLH

更新时间: 2022-09-22 09:42:03
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
67页 988K
描述
MC56F844xx Advance

56F84462VLH 数据手册

 浏览型号56F84462VLH的Datasheet PDF文件第3页浏览型号56F84462VLH的Datasheet PDF文件第4页浏览型号56F84462VLH的Datasheet PDF文件第5页浏览型号56F84462VLH的Datasheet PDF文件第7页浏览型号56F84462VLH的Datasheet PDF文件第8页浏览型号56F84462VLH的Datasheet PDF文件第9页 
Overview  
• 32-bit arithmetic and logic multi-bit shifter  
• Four 36-bit accumulators, including extension bits  
• Parallel instruction set with unique DSP addressing modes  
• Hardware DO and REP loops  
• Bit reverse address mode, effectively supporting DSP and Fast Fourier Transform  
algorithms  
• Full shadowing of the register stack for zero-overhead context saves and restores:  
nine shadow registers corresponding to the R0, R1, R2, R3, R4, R5, N, N3, and M01  
address registers  
• Instruction set supporting both DSP and controller functions  
• Controller-style addressing modes and instructions for compact code  
• Enhanced bit manipulation instruction set  
• Efficient C compiler and local variable support  
• Software subroutine and interrupt stack with depth limited only by memory  
• Priority level setting for interrupt levels  
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging  
that is independent of processor speed  
1.3 Operation Parameters  
• Up to 60 MHz operation at -40 °C to 105 °C ambient temperature  
• Single 3.3 V power supply  
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V  
1.4 On-Chip Memory and Memory Protection  
• Modified dual Harvard architecture permits as many as three simultaneous accesses  
to program and data memory  
• Internal flash memory with security and protection to prevent unauthorized access  
• Memory resource protection (MRP) unit to protect supervisor programs and  
resources from user programs  
• Programming code can reside in flash memory during flash programming  
• The dual-ported RAM controller supports concurrent instruction fetches and data  
accesses, or dual data accesses, by the DSC core.  
• Concurrent accesses provide increased performance.  
• The data and instruction arrive at the core in the same cycle, reducing latency.  
• On-chip memory  
• Up to 128 KW program/data flash memory  
• Up to 16 KW dual port data/program RAM  
MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012.  
6
Freescale Semiconductor, Inc.  
Preliminary  
General Business Information  

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